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三段式Verilog的IDE程序，但只有DMA部分，需要自己添加PIO的代碼
上傳時間： 2014-01-04
上傳用戶：familiarsmile
本文描述可升級的DMR系統(tǒng)的數(shù)據(jù)協(xié)議包（PDP），該系統(tǒng)包含三級可能的產(chǎn)品： 第一級產(chǎn)品：DMA設備使用完整的天線，工作在直通模式（不使用基礎設施通信）的DMR設備，有普通授權(quán)而沒有個體授權(quán)
標簽： DMR PDP 數(shù)據(jù)協(xié)議
上傳時間： 2013-11-28
上傳用戶：CHINA526
DOS下的CDROM讀寫加速驅(qū)動，使用DMA進行加速讀寫操作
上傳時間： 2014-01-20
上傳用戶：qazxsw
pci9054的驅(qū)動，主要用于高速DMA的傳輸
上傳時間： 2017-06-05
上傳用戶：stvnash
嵌入式系統(tǒng)基本驅(qū)動，對硬件寄存器進行初始化還有給設備分配I/O，申請DMA通道等
標簽： 嵌入式系統(tǒng) 驅(qū)動
上傳時間： 2017-06-12
上傳用戶：anng
This manual describes SAMSUNG s S3C2410A 16/32-bit RISC microprocessor. This product is designed to provide hand-held devices and general applications with cost-effective, low-power, and high-performance micro-controller solution in small die size. To reduce total system cost, the S3C2410A includes the following components separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD Controller (STN & TFT), NAND Flash Boot Loader, System Manager (chip select logic and SDRAM Controller), 3-ch UART, 4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch Screen Interface, IIC-BUS Interface, IIS-BUS Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface, 2-ch SPI and PLL for clock generation.
標簽： This microprocessor describes S3C2410A
上傳時間： 2013-11-30
上傳用戶：GavinNeko
dsPIC33F型號的CPU可配置10位或12位的ADC采樣，轉(zhuǎn)換完成后直接從DMA中讀取轉(zhuǎn)換結(jié)果。源碼中對多路模擬量進行采樣，對ADC及DMA分別進行了配置。
上傳時間： 2014-01-23
上傳用戶：sy_jiadeyi
very comprehensive example, windows WDM driver development ex The use of drive technology can s Say all ?� � e full speed equipm STM32 DAC DMA TIXINGBO Implement hiding process, make pr dma ddk driver
標簽： comprehensive development technology example
上傳時間： 2013-12-22
上傳用戶：蟲蟲蟲蟲蟲蟲
very comprehensive example, windows WDM driver development ex The use of drive technology can s Say all � � e full speed equipm STM32 DAC DMA TIXINGBO Implement hiding process, make pr dma ddk driver
標簽： comprehensive development technology example
上傳時間： 2013-12-14
上傳用戶：alan-ee
Wishbone to LPC (Low-Pin Count) Bridge, includes master and slave modules. Supports 8-bit I/O Read and Write cycles, 8-bit Memory Read/Write cycles, DMA cycles, and up to 32-bit Firmware memory read/write cycles. Serial IRQ support is also provided. None of this has been tested (yet) with a third-party LPC Peripheral or Host.
標簽： Wishbone Supports includes Low-Pin
上傳時間： 2014-12-20
上傳用戶：古谷仁美
