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Abstract: standard PCB design and mounting processes can adversely influence MEMS inertial sensors.This application note contains guidelines for the layout, soldering, and mounting of MEMS inertialsensors in LGA packages in order to reduce stresses and improve functionality.
上傳時(shí)間： 2014-01-15
上傳用戶：sjb555
AWG=American Wire Gauge standard：Gauge Diam Area R I at 3A/mm2 AWGmm mm2 ohm/km mA
上傳時(shí)間： 2013-11-08
上傳用戶：yangqian
A Computer-On-Module, or COM, is a Module with all components necessary for a bootable host computer, packaged as a super component. A COM requires a Carrier Board to bring out I/O and to power up. COMs are used to build single board computer solutions and offer OEMs fast time-to-market with reduced development cost. Like integrated circuits, they provide OEMs with significant freedom in meeting form-fit-function requirements. For all these reasons the COM methodology has gained much popularity with OEMs in the embedded industry. COM Express® is an open industry standard for Computer-On-Modules. It is designed to be future proof and to provide a smooth transition path from legacy parallel interfaces to LVDS (Low Voltage Differential Signaling) interfaces. These include the PCI bus and parallel ATA on the one hand and PCI Express and Serial ATA on the other hand.
上傳時(shí)間： 2013-11-05
上傳用戶：Wwill
With the Altera Nios II embedded processor, you as the system designercan accelerate time-critical software algorithms by adding custominstructions to the Nios II processor instruction set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andcomputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II processor
上傳時(shí)間： 2013-11-07
上傳用戶：swing
Abstract: This application note discusses a design for a phantom antenna power-supply system compatible with theDigital Satellite Equipment Control (DiSEqC) communication standard, using the MAX16948 automotive dual, highvoltageLDO/switch. The presented application circuit provides a remote antenna power supply and also enables onewaycommunication from the radio head unit to the remote antenna. This system architecture offers flexibility inDiSEqC tone-burst frequency choice (100Hz to 30kHz), enabling users the ability to select the best frequency for theirapplication.
標(biāo)簽： 數(shù)字衛(wèi)星 控制 兼容 供電系統(tǒng)設(shè)計(jì)
上傳時(shí)間： 2013-11-17
上傳用戶：fnhhs
Abstract: While many questions still surround the creation and deployment of the smart grid, the need for a reliablecommunications infrastructure is indisputable. Developers of the IEEE 1901.2 standard identified difficult channel conditionscharacteristic of low-frequency powerline communications and implemented an orthogonal frequency division multiplexing (OFDM)architecture using advanced modulation and channel-coding techniques. This strategy helped to ensure a robust communicationsnetwork for the smart grid.
標(biāo)簽： 1901.2 OFDM IEEE 正交頻分復(fù)用
上傳時(shí)間： 2013-10-18
上傳用戶：myworkpost
Abstract: This article describes the Antenna Interface standards Group (AISG) standard in telecommunications and details itshardware implementation. It explains how a fully integrated transceiver such as the MAX9947 can help reduce space and cost, andsolve bus arbitrations in base-station tower equipment.
標(biāo)簽： AISG 硬件 分立收發(fā)器 控制系統(tǒng)
上傳時(shí)間： 2014-12-30
上傳用戶：wangchong
針對(duì)UHF讀寫器設(shè)計(jì)中，在符合EPC Gen2標(biāo)準(zhǔn)的情況下，對(duì)標(biāo)簽返回的高速數(shù)據(jù)進(jìn)行正確解碼以達(dá)到正確讀取標(biāo)簽的要求，提出了一種新的在ARM平臺(tái)下采用邊沿捕獲統(tǒng)計(jì)定時(shí)器數(shù)判斷數(shù)據(jù)的方法，并對(duì)FM0編碼進(jìn)行解碼。與傳統(tǒng)的使用定時(shí)器定時(shí)采樣高低電平的FM0解碼方法相比，該解碼方法可以減少定時(shí)器定時(shí)誤差累積的影響；可以將捕獲定時(shí)器數(shù)中斷與數(shù)據(jù)判斷解碼相對(duì)分隔開，使得中斷對(duì)解碼影響很小，實(shí)現(xiàn)捕獲與解碼的同步。通過實(shí)驗(yàn)表明，這種方法提高了解碼的效率，在160 Kb/s的接收速度下，讀取一張標(biāo)簽的時(shí)間約為30次/s。 Abstract: Aiming at the requirement of receiving correctly decoded data from the tag under high-speed communication which complied with EPC Gen2 standard in the design of UHF interrogator， the article introduced a new technology for FM0 decoding which counted the timer counter to judge data by using the edge interval of signal capture based on the ARM7 platform. Compared with the traditional FM0 decoding method which used the timer timed to sample the high and low level， the method could reduce the accumulation of timing error and could relatively separate capture timer interrupt and the data judgment for decoding， so that the disruption effect on the decoding was small and realizd synchronization of capture and decoding. Testing result shows that the method improves the efficiency of decoding， at 160 Kb/s receiving speed， the time of the interrogator to read a tag is about 30 times/s.
標(biāo)簽： UHF FM0 讀寫器 解碼技術(shù)
上傳時(shí)間： 2013-11-10
上傳用戶：liufei
解壓密碼：www.elecfans.com 隨著微電子技術(shù)的迅速發(fā)展以及集成電路規(guī)模不斷提高，對(duì)電路性能的設(shè)計(jì) 要求越來越嚴(yán)格，這勢(shì)必對(duì)用于大規(guī)模集成電路設(shè)計(jì)的EDA 工具提出越來越高的 要求。自1972 年美國加利福尼亞大學(xué)柏克萊分校電機(jī)工程和計(jì)算機(jī)科學(xué)系開發(fā) 的用于集成電路性能分析的電路模擬程序SPICE（Simulation Program with IC Emphasis）誕生以來，為適應(yīng)現(xiàn)代微電子工業(yè)的發(fā)展，各種用于集成電路設(shè)計(jì)的 電路模擬分析工具不斷涌現(xiàn)。HSPICE 是Meta-Software 公司為集成電路設(shè)計(jì)中 的穩(wěn)態(tài)分析，瞬態(tài)分析和頻域分析等電路性能的模擬分析而開發(fā)的一個(gè)商業(yè)化通 用電路模擬程序，它在柏克萊的SPICE（1972 年推出），MicroSim公司的PSPICE （1984 年推出）以及其它電路分析軟件的基礎(chǔ)上，又加入了一些新的功能，經(jīng) 過不斷的改進(jìn)，目前已被許多公司、大學(xué)和研究開發(fā)機(jī)構(gòu)廣泛應(yīng)用。HSPICE 可 與許多主要的EDA 設(shè)計(jì)工具，諸如Candence,Workview 等兼容，能提供許多重要 的針對(duì)集成電路性能的電路仿真和設(shè)計(jì)結(jié)果。采用HSPICE 軟件可以在直流到高 于100MHz 的微波頻率范圍內(nèi)對(duì)電路作精確的仿真、分析和優(yōu)化。在實(shí)際應(yīng)用中， HSPICE能提供關(guān)鍵性的電路模擬和設(shè)計(jì)方案，并且應(yīng)用HSPICE進(jìn)行電路模擬時(shí)， 其電路規(guī)模僅取決于用戶計(jì)算機(jī)的實(shí)際存儲(chǔ)器容量。 The HSPICE Integrator Program enables qualified EDA vendors to integrate their products with the de facto standard HSPICE simulator, HSPICE RF simulator, and WaveView Analyzer™. In addition, qualified HSPICE Integrator Program members have access to HSPICE integrator application programming interfaces (APIs). Collaboration between HSPICE Integrator Program members will enable customers to achieve more thorough design verification in a shorter period of time from the improvements offered by inter-company EDA design solutions.
標(biāo)簽： download hspice 2007
上傳時(shí)間： 2013-11-10
上傳用戶：123312
本軟件是關(guān)于MAX338, MAX339的英文數(shù)據(jù)手冊(cè)：MAX338, MAX339 8通道/雙4通道、低泄漏、CMOS模擬多路復(fù)用器 The MAX338/MAX339 are monolithic, CMOS analog multiplexers (muxes). The 8-channel MAX338 is designed to connect one of eight inputs to a common output by control of a 3-bit binary address. The dual, 4-channel MAX339 is designed to connect one of four inputs to a common output by control of a 2-bit binary address. Both devices can be used as either a mux or a demux. On-resistance is 400Ω max, and the devices conduct current equally well in both directions. These muxes feature extremely low off leakages (less than 20pA at +25°C), and extremely low on-channel leakages (less than 50pA at +25°C). The new design offers guaranteed low charge injection (1.5pC typ) and electrostatic discharge (ESD) protection greater than 2000V, per method 3015.7. These improved muxes are pin-compatible upgrades for the industry-standard DG508A and DG509A. For similar Maxim devices with lower leakage and charge injection but higher on-resistance, see the MAX328 and MAX329.
上傳時(shí)間： 2013-11-12
上傳用戶：18711024007
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