This application note provides step-by-step instructions on how to recreate a Tri-Mode Ethernet(TEMAC) performance testing system using the ML405 board and MontaVista Linux 4.0. Thisapplication note shows how to set up a simple EDK Base System Builder system on the ML405Evaluation Platform and run performance tests. The network architecture for the test isdescribed. A system is built and downloaded into the FPGA. A MontaVista Linux kernel isconfigured, built, and downloaded into the ML405 Evaluation Platform. The instructions forobtaining and setting up the software used to perform the measurements, netperf, are given.
標(biāo)簽： Virtex TEMAC XAPP 1023
上傳時(shí)間： 2013-11-11
上傳用戶：saharawalker
The #1 Step-by-Step Guide to labviewNow Completely Updated for labview 8! Master labview 8 with the industry's friendliest, most intuitive tutorial: labview for Everyone, Third Edition. Top labview experts Jeffrey Travis and Jim Kring teach labview the easy way: through carefully explained, step-by-step examples that give you reusable code for your own projects! This brand-new Third Edition has been fully revamped and expanded to reflect new features and techniques introduced in labview 8. You'll find two new chapters, plus dozens of new topics, including Project Explorer, AutoTool, XML, event-driven programming, error handling, regular expressions, polymorphic VIs, timed structures, advanced reporting, and much more. Certified labview Developer (CLD) candidates will find callouts linking to key objectives on NI's newest exam, making this book a more valuable study tool than ever. Not just what to d why to do it! Use labview to build your own virtual workbench Master labview's foundations: wiring, creating, editing, and debugging VIs; using controls and indicators; working with data structures; and much more Learn the "art" and best practices of effective labview development NEW: Streamline development with labview Express VIs NEW: Acquire data with NI-DAQmx and the labview DAQmx VIs NEW: Discover design patterns for error handling, control structures, state machines, queued messaging, and more NEW: Create sophisticated user interfaces with tree and tab controls, drag and drop, subpanels, and more Whatever your application, whatever your role, whether you've used labview or not, labview for Everyone, Third Edition is the fastest, easiest way to get the results you're after!
標(biāo)簽： Everyone LabVIEW for 英文
上傳時(shí)間： 2013-10-14
上傳用戶：shawvi
Abstract: This application note helps system designers choose the correct external components for use with the MAX16948 dualremote antenna LDO/switch, thus ensuring that automobile-regulated phantom antenna supply and output-current-monitoring circuitrymeet performance objectives. An electronic calculator is provided that helps specify the critical external components for theMAX16948, thus reducing design time. The calculator also determines the device's analog output voltage, output current-limitthreshold, and output current-sensing accuracies. The calculator includes new automatic Step By Step feature that assists designerswith component choice. To use the new automatic feature, click on the Step By Step button relative to the desired section.
上傳時(shí)間： 2013-11-04
上傳用戶：lhll918
XRP7714是一款四輸出脈寬調(diào)制（PWM）分級(jí)降壓（step down）DC-DC控制器，并具有內(nèi)置LDO提供待機(jī)電源。該器件在單個(gè)IC上為電池供電的產(chǎn)品提供了整套的電源管理方案，并且通過(guò)內(nèi)含的I2C串行接口進(jìn)行整體的編程配置
標(biāo)簽： 7714 XRP PWM 數(shù)字
上傳時(shí)間： 2013-11-01
上傳用戶：xiaohuanhuan
《西門子系列PLC原理及應(yīng)用》共有8章，第1章介紹了PLC的基本組成與工作原理；第2章介紹了西門子S7-200系列PLC的構(gòu)成、性能及其工作方式；第3章詳細(xì)地介紹了S7-200系列PLC專用編程軟件STEP 7-Micro/WIN的主要功能與使用方法；第4～5章，結(jié)合實(shí)例介紹S7-200系列PLC的基本命令與功能命令；第6章講述了S7-200系列PLC的網(wǎng)絡(luò)通信知識(shí)與命令；第7章講述了PLC控制系統(tǒng)的總體設(shè)計(jì)方法，并由淺入深地介紹了8個(gè)控制系統(tǒng)設(shè)計(jì)實(shí)例；第8章介紹了西門子S7-200系列PLC的安裝與維護(hù)。
上傳時(shí)間： 2013-12-31
上傳用戶：stampede
MAXQUSBJTAGOW評(píng)估板軟件:關(guān)鍵特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
標(biāo)簽： MAXQUSBJTAGOW 評(píng)估板 軟件
上傳時(shí)間： 2013-10-24
上傳用戶：teddysha
MAXQUSBJTAGOW評(píng)估板軟件:關(guān)鍵特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
標(biāo)簽： MAXQUSBJTAGOW 評(píng)估板 軟件
上傳時(shí)間： 2013-11-23
上傳用戶：truth12
附件為：pdf轉(zhuǎn)cad軟件最新版 PDF Fly V7.1安裝文件。還附有自制的Crack，把我的文件 貼到裝好的目錄下就行了!沒(méi)有30天限制。 附pdf轉(zhuǎn)cad軟件使用教程： 1、pdf轉(zhuǎn)cad軟件的界面比較簡(jiǎn)單的，如下圖，點(diǎn)擊ADD添加你要轉(zhuǎn)換的PDF文件，然后下一步 2、選擇DXF格式，然后在右邊的option里面還可以進(jìn)行相關(guān)的設(shè)置 3、然后再下一步。step 3頁(yè)面只要點(diǎn)最下面的 convert 就可以了 轉(zhuǎn)完以后同樣線條沒(méi)有什么大問(wèn)題的，只是文字肯定是被打碎的，你自己需要?jiǎng)h除后重新輸入要重新輸入。
上傳時(shí)間： 2013-10-22
上傳用戶：ardager
Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.
上傳時(shí)間： 2013-10-22
上傳用戶：aeiouetla
PCB設(shè)計(jì)問(wèn)題集錦 問(wèn)：PCB圖中各種字符往往容易疊加在一起，或者相距很近，當(dāng)板子布得很密時(shí)，情況更加嚴(yán)重。當(dāng)我用Verify Design進(jìn)行檢查時(shí)，會(huì)產(chǎn)生錯(cuò)誤，但這種錯(cuò)誤可以忽略。往往這種錯(cuò)誤很多，有幾百個(gè)，將其他更重要的錯(cuò)誤淹沒(méi)了，如何使Verify Design會(huì)略掉這種錯(cuò)誤，或者在眾多的錯(cuò)誤中快速找到重要的錯(cuò)誤。 答：可以在顏色顯示中將文字去掉,不顯示后再檢查;并記錄錯(cuò)誤數(shù)目。但一定要檢查是否真正屬于不需要的文字。 問(wèn)： What’s mean of below warning:(6230,8330 L1) Latium Rule not checked: COMPONENT U26 component rule.答：這是有關(guān)制造方面的一個(gè)檢查，您沒(méi)有相關(guān)設(shè)定，所以可以不檢查。 問(wèn)： 怎樣導(dǎo)出jop文件？答：應(yīng)該是JOB文件吧？低版本的powerPCB與PADS使用JOB文件。現(xiàn)在只能輸出ASC文件，方法如下STEP：FILE/EXPORT/選擇一個(gè)asc名稱/選擇Select ALL/在Format下選擇合適的版本/在Unit下選Current比較好/點(diǎn)擊OK/完成然后在低版本的powerPCB與PADS產(chǎn)品中Import保存的ASC文件，再保存為JOB文件。 問(wèn)： 怎樣導(dǎo)入reu文件？答：在ECO與Design 工具盒中都可以進(jìn)行，分別打開(kāi)ECO與Design 工具盒，點(diǎn)擊右邊第2個(gè)圖標(biāo)就可以。 問(wèn)： 為什么我在pad stacks中再設(shè)一個(gè)via:1(如附件）和默認(rèn)的standardvi(如附件）在布線時(shí)V選擇1，怎么布線時(shí)按add via不能添加進(jìn)去這是怎么回事，因?yàn)橛袝r(shí)要使用兩種不同的過(guò)孔。答：PowerPCB中有多個(gè)VIA時(shí)需要在Design Rule下根據(jù)信號(hào)分別設(shè)置VIA的使用條件，如電源類只能用Standard VIA等等，這樣操作時(shí)就比較方便。詳細(xì)設(shè)置方法在PowerPCB軟件通中有介紹。 問(wèn)：為什么我把On-line DRC設(shè)置為prevent..移動(dòng)元時(shí)就會(huì)彈出(圖2),而你們教程中也是這樣設(shè)置怎么不會(huì)呢?答：首先這不是錯(cuò)誤,出現(xiàn)的原因是在數(shù)據(jù)中沒(méi)有BOARD OUTLINE.您可以設(shè)置一個(gè),但是不使用它作為CAM輸出數(shù)據(jù). 問(wèn)：我用ctrl+c復(fù)制線時(shí)怎設(shè)置原點(diǎn)進(jìn)行復(fù)制，ctrl+v粘帖時(shí)總是以最下面一點(diǎn)和最左邊那一點(diǎn)為原點(diǎn) 答： 復(fù)制布線時(shí)與上面的MOVE MODE設(shè)置沒(méi)有任何關(guān)系,需要在右鍵菜單中選擇,這在PowerPCB軟件通教程中有專門介紹. 問(wèn)：用(圖4)進(jìn)行修改線時(shí)拉起時(shí)怎總是往左邊拉起(圖5)，不知有什么辦法可以輕易想拉起左就左，右就右。答： 具體條件不明,請(qǐng)檢查一下您的DESIGN GRID,是否太大了. 問(wèn)： 好不容易拉起右邊但是用(圖6)修改線怎么改怎么下面都會(huì)有一條不能和在一起，而你教程里都會(huì)好好的(圖8)答：這可能還是與您的GRID 設(shè)置有關(guān),不過(guò)沒(méi)有問(wèn)題,您可以將不需要的那段線刪除.最重要的是需要找到布線的感覺(jué),每個(gè)軟件都不相同,所以需要多練習(xí)。 問(wèn)： 尊敬的老師:您好！這個(gè)圖已經(jīng)畫好了，但我只對(duì)（如圖1）一種的完全間距進(jìn)行檢查，怎么錯(cuò)誤就那么多，不知怎么改進(jìn)。請(qǐng)老師指點(diǎn)。這個(gè)圖在附件中請(qǐng)老師幫看一下，如果還有什么問(wèn)題請(qǐng)指出來(lái)，本人在改進(jìn)。謝！！！！！答：請(qǐng)注意您的DRC SETUP窗口下的設(shè)置是錯(cuò)誤的,現(xiàn)在選中的SAME NET是對(duì)相同NET進(jìn)行檢查,應(yīng)該選擇NET TO ALL.而不是SAME NET有關(guān)各項(xiàng)參數(shù)的含義請(qǐng)仔細(xì)閱讀第5部教程. 問(wèn)： U101元件已建好，但元件框的拐角處不知是否正確，請(qǐng)幫忙CHECK 答：元件框等可以通過(guò)修改編輯來(lái)完成。問(wèn)： U102和U103元件沒(méi)建完全，在自動(dòng)建元件參數(shù)中有幾個(gè)不明白：如：SOIC--》silk screen欄下spacing from pin與outdent from first pin對(duì)應(yīng)U102和U103元件應(yīng)寫什么數(shù)值，還有這兩個(gè)元件SILK怎么自動(dòng)設(shè)置，以及SILK內(nèi)有個(gè)圓圈怎么才能畫得與該元件參數(shù)一致。 答：Spacing from pin指從PIN到SILK的Y方向的距離,outdent from first pin是第一PIN與SILK端點(diǎn)間的距離.請(qǐng)根據(jù)元件資料自己計(jì)算。
標(biāo)簽： PCB 設(shè)計(jì)問(wèn)題 集錦
上傳時(shí)間： 2014-01-03
上傳用戶：Divine
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