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ADS 集成開發環境是ARM 公司推出的ARM 核微控制器集成開發工具，英文全稱為ARM Developer suite，成熟版本為ADS1.2。ADS1.2 支持ARM10 之前的所有ARM 系列微控制器，支持軟件調試及JTAG 硬件仿真調試，支持匯編、C、C++源程序，具有編譯效率高、系統庫功能強等特點，可以在Windows98、Windows XP、Windows2000 以及RedHat Linux上運行。這里將簡單介紹使用 ADS1.2 建立工程，編譯連接設置，調試操作等等。最后還介紹了基于LPC2100 系列ARM7 微控制器的工程模板的使用，EasyJTAG 仿真器的安裝與使用。
上傳時間： 2013-11-18
上傳用戶：pol123
Multisim11.0
標簽： Multisim Circuit Design suite
上傳時間： 2013-11-18
上傳用戶：彭玖華
Multisim11.0
標簽： Multisim Circuit Design suite
上傳時間： 2013-10-28
上傳用戶：不懂夜的黑
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-21
上傳用戶：wxqman
ADS教程 在這一章里，將介紹ARM 開發軟件ADS(ARM Developer suite)。通過學習如何在CodeWarrior IDE 集成開發環境下編寫，編譯一個工程的例子，使讀者能夠掌握在ADS 軟件平臺下開發用戶應用 程序。本章還描述了如何使用AXD 調試工程，使讀者對于調試工程有個初步的理解，為進一步的 使用和掌握調試工具起到拋磚引玉的作用
上傳時間： 2013-12-24
上傳用戶：小寶愛考拉
簡易手機軟件系統，具有話音，短信等基本業務處理功能，用Telelogic Tau SDL and TTCN suite 4.4完成，含完整開發文檔，已編譯通過
標簽： 手機軟件
上傳時間： 2015-03-30
上傳用戶：rocketrevenge
ADS1.2是一個使用方便的集成開發環境，全稱是ARM developer suite v1.2。它是由arm公司提供的專門用于arm相關應用開發和調試的綜合性軟件。
上傳時間： 2013-12-24
上傳用戶：c12228
Nucleus GRAFIX Porting Guide，本文檔包括Toolset Errors and Warnings 、 Display Device Initialization Display Device Drivers、 Test suite and Demo Program Modifications
標簽： Nucleus Porting GRAFIX Guide
上傳時間： 2013-12-20
上傳用戶：sk5201314
A complete business intelligence platform that includes reporting, analysis (OLAP), dashboards, data mining and data integration (ETL). Use it as a full suite or as individual components that are accessible via web services. Ranked #1 in open source BI.
標簽： intelligence dashboards reporting complete
上傳時間： 2015-09-11
上傳用戶：離殤
This document describes the uIP TCP/IP stack. The uIP TCP/IP stack is an extremely small implementation of the TCP/IP protocol suite intended for embedded systems running low-end 8 or 16-bit microcon-trollers. The code size and RAM requirements of uIP is an order of magnitude smaller than other generic TCP/IP stacks today.
標簽： stack implementat TCP describes
上傳時間： 2015-09-18
上傳用戶：zsjinju
