The cable compensation system is an experiment system that performs simulations of partial or microgravity environments on earth. It is a highly nonlinear and complex system.In this paper, a network based on the theory of the Fuzzy Cerebellum Model Articulation Controller(FCMAC) is proposed to control this cable compensation system. In FCMAC ,without appropriate learning rate, the control system based on FCMAC will become unstable or its convergence speed will become slow.In order to guarantee the convergence of tracking error, we present a new kind of optimization based on adaptive GA for selecting learning rate.Furthermore, this approach is evaluated and its performance is discussed.The simulation results shows that performance of the FCMAC based the proposed method is stable and more effective.
標簽： system compensation simulations experiment
上傳時間： 2015-08-26
上傳用戶：希醬大魔王
ST7529液晶驅動 The ST7529 is a driver & controller LSI for 32 gray scale graphic dot-matrix liquid crystal display systems. It generates 255 Segment and 160 Common driver circuits. This chip is connected directly to a microprocessor, accepts Serial Peripheral Interface (SPI), 8-bit/16-bit parallel or IIC display data and stores in an on-chip display data RAM. It performs display data RAM read/write operation with no external operating clock to minimize power consumption. In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
標簽： 7529 controller dot-matrix graphic
上傳時間： 2013-12-02
上傳用戶：奇奇奔奔
西安電子科技大學 碩士學位論文 《基于DSP的無刷直流電機高性能調速系統的研究》 作者姓名：張焱 Research on BLDC High Performance Speed-adjusting System Based on DSP
標簽： Speed-adjusti Performance Research BLDC
上傳時間： 2016-08-18
上傳用戶：日光微瀾
ST7787 芯片的SPEC，比亞迪2.4inchLCM的SPEC。The ST7787 is a single-chip controller/driver for 262K-color, graphic type TFT-LCD. It consists of 720 source line and 320 gate line driving circuits. This chip is capable of connecting directly to an external microprocessor, and accepts Serial Peripheral Interface (SPI), 8-bits/9-bits/16-bits/18-bits parallel interface. Display data can be stored in the on-chip display data RAM of 240x320x18 bits. It can perform display data RAM read/write operation with no external operation clock to minimize power consumption. In addition, because of the integrated power supply circuits necessary to drive liquid crystal, it is possible to make a display system with the fewest components.
上傳時間： 2016-09-22
上傳用戶：woshini123456
This is schematic and Gerber files of PCB that is used for GSM alarm system. This is industrial-grade system with many features like 1-wire (iButton) interface, additional interface for video camera (UART JPEG camera is used), SD card to store pictures from camera and send them by GSM to remote mobile phone. Can be used as a reference design for anyone who wants to make own GSM alarm system system based on SIM300C module from Simcom.
標簽： This industrial-grad schematic is
上傳時間： 2013-12-06
上傳用戶：com1com2
The STi7105 uses state of the art process technology to provide an ultra low-cost, fully featured HD AVC decoder IC. It is a highly integrated system-on-chip suitable for STB markets across all networks (cable/satellite/DTT/x- DSL/IP) worldwide
標簽： technology low-cost featured process
上傳時間： 2013-12-22
上傳用戶：時代電子小智
Genode FX is a composition of hardware and software components that enable the creation of fully fledged graphical user interfaces as system-on-chip solutions using commodity FPGAs.
標簽： composition components hardware creation
上傳時間： 2017-09-24
上傳用戶：huql11633
?ARINC429總線協議是美國航空電子工程委員會(Airlines Engineering Committee)于1977年7月提出的，并于同年發表并獲得批準使用，它的全稱是數字式信息傳輸系統(Digital Information Transmission System ) 。協議標準規定了航空電子設備及有關系統間的數字信息傳輸要求。ARINC429廣泛應用在先進的民航客機中，如B-737、B-757、B-767，俄制軍用飛機也選用了類似的技術。
標簽： ARINC429 總線
上傳時間： 2015-03-25
上傳用戶：423619775
A design about 8051 (running at 12MHz) based system with 3 7-Seg displays and two buttons to implement the following functions. 1. When press the + button, the display C = A+B. 2. When press the button, the display C = A - B. “A” and “B” are 8-bit inputs when “C” is 9-bit output.
上傳時間： 2015-05-05
上傳用戶：guoxiy
The TAS3204 is a highly-integrated audio system-on-chip (SOC) consisting of a fully-programmable, 48-bit digital audio processor, a 3:1 stereo analog input MUX, four ADCs, four DACs, and other analog functionality. The TAS3204 is programmable with the graphical PurePath Studio? suite of DSP code development software. PurePath Studio is a highly intuitive, drag-and-drop environment that minimizes software development effort while allowing the end user to utilize the power and flexibility of the TAS3204’s digital audio processing core. TAS3204 processing capability includes speaker equalization and crossover, volume/bass/treble control, signal mixing/MUXing/splitting, delay compensation, dynamic range compression, and many other basic audio functions. Audio functions such as matrix decoding, stereo widening, surround sound virtualization and psychoacoustic bass boost are also available with either third-party or TI royalty-free algorithms. The TAS3204 contains a custom-designed, fully-programmable 135-MHz, 48-bit digital audio processor. A 76-bit accumulator ensures that the high precision necessary for quality digital audio is maintained during arithmetic operations. Four differential 102 dB DNR ADCs and four differential 105 dB DNR DACs ensure that high quality audio is maintained through the whole signal chain as well as increasing robustness against noise sources such as TDMA interference. The TAS3204 is composed of eight functional blocks: Clocking System Digital Audio Interface Analog Audio Interface Power supply Clocks, digital PLL I2C control interface 8051 MCUcontroller Audio DSP – digital audio processing 特性 Digital Audio Processor Fully Programmable With the Graphical, Drag-and-Drop PurePath Studio? Software Development Environment 135-MHz Operation 48-Bit Data Path With 76-Bit Accumulator Hardware Single-Cycle Multiplier (28 × 48)
上傳時間： 2016-05-06
上傳用戶：fagong
