As logic systems get larger and more complex, theirsupply current requirements continue to rise. Systemsrequiring 100A are fairly common. A high current powersupply to meet such requirements usually requires parallelingseveral power regulators to alleviate the thermalstress on the individual power components. A powersupply designer is left with the choice of how to drive theseparalleled regulators: brute-force single-phase or smartPolyPhaseTM.
上傳時間： 2013-10-08
上傳用戶：zhqzal1014
Notebook and palmtop systems need a multiplicity ofregulated voltages developed from a single battery. Smallsize, light weight, and high efficiency are mandatory forcompetitive solutions in this area. Small increases inefficiency extend battery life, making the final productmuch more usable with no increase in weight. Additionally,high efficiency minimizes the heat sinks needed onthe power regulating components, further reducing systemweight and size.
上傳時間： 2013-11-11
上傳用戶：大三三
為了改變目前電網現場作業管理的變電巡檢、變電檢修試驗、輸電線路巡檢檢修等管理系統各自獨立運行，信息不能共享，功能、效率受限，建設和維護成本高的現狀，提出了采用B/S+C/S構架模式，將各現場作業管理模塊和生產MIS（管理系統）集成為一體的現場作業管理系統的設計方案，做到各子系統和生產MIS軟硬資源共享，做到同一數據唯一入口、一處錄入多處使用。各子系統設備人員等基礎信息來源于生產管理系統，各子系統又是生產管理系統的作業數據、缺陷信息的重要來源。經過研究試用成功和推廣應用，目前該系統已在江西電網220 kV及以上變電站全面應用。 Abstract: In order to improve the status that the substation field inspection system， substation equipments maintenance and testing system， power-line inspection and maintenance system are running independent with each other. They can?蒺t share the resource information which accordingly constrains their functions and efficiency， and their construction and maintenance costs are high. This paper introduces a field standardized work management system based on B/S+C/S mode， integrating all field work management systems based on MIS and share the equipments and employee?蒺s data of MIS，the field work data of the sub systems are the source information of MIS， by which the same single data resouce with one-time input can be utilized in multiple places. After the research and testing， this system is triumphantly using in all 220kV and above substations in Jiangxi grid.
上傳時間： 2013-11-15
上傳用戶：han_zh
數字控制的交流調速系統所選用的微處理器、功率器件及產生PWM波的方法是影響交流調速系統性能好壞的直接因素。在介紹了正弦脈寬調制(SPWM)技術的基礎上，設計了一種以8098單片機作為控制器，以智能功率模塊IPM為開關器件的變頻調速系統。通過軟件編程，產生正弦脈沖寬度調制波形來控制絕緣柵雙極晶體管的導通和關斷，從而達到控制異步電動機轉速的目的。實驗結果表明，該系統可調頻率調電壓，穩定度高，調速范圍寬，具有較強的實用價值 Abstract: AC variable speed with digital control systems used microprocessors， power devices and generate PWM wave is the direct factors of affecting the performance AC speed regulation system. On the basis of introducing the sinusoidal pulse width modulation (SPWM) technology，this paper designed variable speed system which used 8098 as a controller， intelligent power module IPM as switching device. Through software programming， resulting in sinusoidal pulse width modulation waveform to control the insulated gate bipolar transistor turn on and off， so as to achieve the purpose of speed control of induction motors. Experimental results show that the system can adjust frequency modulation voltage， high stability， wide speed range， has a strong practical value.
上傳時間： 2013-11-14
上傳用戶：ynwbosss
介紹了當前普通標記機控制系統現狀及其存在缺點，給出氣動標記機及相頻修正PWM模式的工作原理。采用ATmega16單片機和USB轉換RS232接口器件CH341T實現驅動控制系統與PC的實時通訊，標記控制系統可升級到USB接口。采用基于ATmega16的相頻修正PWM替換555振蕩電路產生的PWM，可直接通過軟件調整PWM信號。使用達林頓三極管TIP122替代直流繼電器驅動高頻電磁閥，使得電磁閥驅動電路簡單，成本低廉。該控制系統已成功應用于氣動標記機。 Abstract: In this paper,the actuality and demerit of the common gas marking machine control systems are described.The operation principle of the gas marking machine and the phase and frequency correct PWM of ATmega16is introduced.The real-time communication between the driving control system and PC by CH341T which its function is translated USB to RS232is realized,the control systems is updated grade to USB interface.The PWM signal can be adjustable by software for the555surge circuit was substituted by the phase and frequency.The high frequency electromagnetic value’s driving circuit by DC relay is replaced by TIP122,therefore,the circuit is become simple and the cost cheap.The control systems has been widely used in gas marking machine.
上傳時間： 2013-10-18
上傳用戶：1427796291
以AVR單片機ATmega8和USB接口器件PDIUSBD12為核心，基于標準的USB1.1協議，設計一種通用USB接口模塊，以滿足嵌入式系統中對USB接口的需求。對模塊的硬件電路或單片機固件程序的硬件接口層稍加修改即可用于其他各種微處理器。該模塊可為各種嵌入式系統增加USB接口,實現與USB主機系統通信。 Abstract: Based on AVR microcontroller ATmega8 and USB interface chip PDIUSBD12, a general USB interface module is designed according to USB1.1 protocol for various requirements of embedded systems. Only with few modifications in circuit or hardware abstract layer of firmware, the module can be used on many types of microprocessors. All kinds of embedded systems can realize high speed and stable communication with USB host systems, owing to the facility of this module.
上傳時間： 2014-01-08
上傳用戶：趙云興
The TJA1042 is a high-speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol controller and the physical two-wire CAN bus.The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing the differential transmit and receive capability to (amicrocontroller with) a CAN protocol controller.
標簽： High-speed transce 1042 TJA
上傳時間： 2014-12-28
上傳用戶：氣溫達上千萬的
The TJA1051 is a high-speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol controller and the physical two-wire CAN bus.The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing differential transmit and receive capability to (amicrocontroller with) a CAN protocol controller.
標簽： High-speed transce 1051 TJA
上傳時間： 2013-10-17
上傳用戶：jisujeke
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-13
上傳用戶：瓦力瓦力hong
XAPP520將符合2.5V和3.3V I/O標準的7系列FPGA高性能I/O Bank進行連接 The I/Os in Xilinx® 7 series FPGAs are classified as either high range (HR) or high performance (HP) banks. HR I/O banks can be operated from 1.2V to 3.3V, whereas HP I/O banks are optimized for operation between 1.2V and 1.8V. In circumstances that require an HP 1.8V I/O bank to interface with 2.5V or 3.3V logic, a range of options can be deployed. This application note describes methodologies for interfacing 7 series HP I/O banks with 2.5V and 3.3V systems
上傳時間： 2013-11-19
上傳用戶：yyyyyyyyyy
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