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中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly enhanced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽：
UltraScale
Xilinx
架構(gòu)
上傳時(shí)間：
2013-11-13
上傳用戶：瓦力瓦力hong
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This white paper discusses how market trends, the need for increased productivity, and new legislation have
accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is
changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to
market. This allows FPGA users to design their own customized safety controllers and provides a significant
competitive advantage over traditional microcontroller or ASIC-based designs.
Introduction
The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in
cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas
around machines such as fast-moving robots, and distributed control systems in process automation equipment such
as those used in petrochemical plants.
The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of
electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing
safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was
developed in the mid-1980s and has been revised several times to cover the technical advances in various industries.
In addition, derivative standards have been developed for specific markets and applications that prescribe the
particular requirements on functional safety systems in these industry applications. Example applications include
process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC
62304), automotive (ISO 26262), power generation, distribution, and transportation.
圖Figure 1. Local Safety System
標(biāo)簽：
FPGA
安全系統(tǒng)
上傳時(shí)間：
2013-11-05
上傳用戶：維子哥哥
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Xilinx FPGAs require at least two power supplies: VCCINTfor core circuitry and VCCO for I/O interface. For the latestXilinx FPGAs, including Virtex-II Pro, Virtex-II and Spartan-3, a third auxiliary supply, VCCAUX may be needed. Inmost cases, VCCAUX can share a power supply with VCCO.The core voltages, VCCINT, for most Xilinx FPGAs, rangefrom 1.2V to 2.5V. Some mature products have 3V, 3.3Vor 5V core voltages. Table 1 shows the core voltagerequirement for most of the FPGA device families. TypicalI/O voltages (VCCO) vary from 1.2V to 3.3V. The auxiliaryvoltage VCCAUX is 2.5V for Virtex-II Pro and Spartan-3, andis 3.3V for Virtex-II.
標(biāo)簽：
Xilinx
FPGA
DC
輸出
上傳時(shí)間：
2013-10-22
上傳用戶：liu999666
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Xilinx Next Generation 28 nm FPGA Technology Overview
Xilinx has chosen 28 nm high-κ metal gate (HKMG) highperformance,low-power process technology and combined it with a new unified ASMBL™ architecture to create a new generation of FPGAs that offer lower power and higher performance. These devices enable unprecedented levels of integration and bandwidth and provide system architects and designers a fully programmable alternative to ASSPs and ASICs.
標(biāo)簽：
Xilinx
FPGA
312
WP
上傳時(shí)間：
2014-12-28
上傳用戶：zhang97080564
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摘 要： 針對非同分布的Nakagami信道，基于矩生成函數(shù)MGF(Moment Generation Function)的分析方法，提出正交空時(shí)分組碼系統(tǒng)STBC(Space-Time Block Coding)的一種快速性能評估算法，不需要涉及超幾何函數(shù)積分運(yùn)算，可在中高信噪比時(shí)，快速準(zhǔn)確地估計(jì)STBC系統(tǒng)的符號錯(cuò)誤概率性能。在平坦瑞利衰落信道下的計(jì)算機(jī)仿真表明，該算法與已有的STBC系統(tǒng)的近似估計(jì)算法相比，具有較優(yōu)的性能。 關(guān)鍵詞： 正交空時(shí)分組碼； MIMO； MGF； 誤符號率
標(biāo)簽：
Nakagami
STBC
分布
上傳時(shí)間：
2014-12-29
上傳用戶：如果你也聽說
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FTTx network architectureThe core technology of optical chips in the FTTx transceiversThe core technology of optical transceiver in FTTxThe trend of Next-generation optical transceiver Technology for FTTx
標(biāo)簽：
Fttx
應(yīng)用于
光模塊
核心
上傳時(shí)間：
2013-10-20
上傳用戶：yoleeson
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The #1 Step-by-Step Guide to labviewNow Completely Updated for labview 8!
Master labview 8 with the industry's friendliest, most intuitive tutorial: labview for Everyone, Third Edition. Top labview experts Jeffrey Travis and Jim Kring teach labview the easy way: through carefully explained, step-by-step examples that give you reusable code for your own projects!
This brand-new Third Edition has been fully revamped and expanded to reflect new features and techniques introduced in labview 8. You'll find two new chapters, plus dozens of new topics, including Project Explorer, AutoTool, XML, event-driven programming, error handling, regular expressions, polymorphic VIs, timed structures, advanced reporting, and much more. Certified labview Developer (CLD) candidates will find callouts linking to key objectives on NI's newest exam, making this book a more valuable study tool than ever.
Not just what to d why to do it!
Use labview to build your own virtual workbench
Master labview's foundations: wiring, creating, editing, and debugging VIs; using controls and indicators; working with data structures; and much more
Learn the "art" and best practices of effective labview development
NEW: Streamline development with labview Express VIs
NEW: Acquire data with NI-DAQmx and the labview DAQmx VIs
NEW: Discover design patterns for error handling, control structures, state machines, queued messaging, and more
NEW: Create sophisticated user interfaces with tree and tab controls, drag and drop, subpanels, and more
Whatever your application, whatever your role, whether you've used labview or not, labview for Everyone, Third Edition is the fastest, easiest way to get the results you're after!
標(biāo)簽：
Everyone
LabVIEW
for
英文
上傳時(shí)間：
2013-10-14
上傳用戶：shawvi
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The NXP LPC314x combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, three channel10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted atconsumer, industrial, medical, and communication markets. To optimize system powerconsumption, the LPC314x have multiple power domains and a very flexible ClockGeneration Unit (CGU) that provides dynamic clock gating and scaling.
標(biāo)簽：
314x
LPC
314
ARM
上傳時(shí)間：
2013-10-11
上傳用戶：yuchunhai1990
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The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
標(biāo)簽：
315x
LPC
315
ARM
上傳時(shí)間：
2014-01-17
上傳用戶：Altman
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It would not be an exaggeration to say that semiconductor devices have transformed humanlife. From computers to communications to internet and video games these devices and the technologies they have enabled have expanded human experience in a way that is unique in history. Semiconductor devices have exploited materials, physics and imaginative applications to spawn new lifestyles. Of course for the device engineer, in spite of the advances, the challenges of reaching higher frequency, lower power consumption, higher power generation etc.
標(biāo)簽：
半導(dǎo)體器件
物理
上傳時(shí)間：
2013-10-28
上傳用戶：songnanhua
