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The TJA1042 is a high-speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol controller and the physical two-wire CAN bus.The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing the differential transmit and receive capability to (amicrocontroller with) a CAN protocol controller.
標簽：
High-speed
transce
1042
TJA
上傳時間：
2014-12-28
上傳用戶：氣溫達上千萬的
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The TJA1051 is a high-speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol controller and the physical two-wire CAN bus.The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing differential transmit and receive capability to (amicrocontroller with) a CAN protocol controller.
標簽：
High-speed
transce
1051
TJA
上傳時間：
2013-10-17
上傳用戶：jisujeke
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The MAX3243E device consists of three line drivers, five line receivers, and a dual charge-pump circuit with±15-kV ESD (HBM and IEC61000-4-2, Air-Gap Discharge) and ±8-kV ESD (IEC61000-4-2, Contact Discharge)protection on serial-port connection pins. The device meets the requirements of TIA/EIA-232-F and provides theelectrical interface between an asynchronous communication controller and the serial-port connector. Thiscombination of drivers and receivers matches that needed for the typical serial port used in an IBM PC/AT, orcompatible. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-Vsupply. In addition, the device includes an always-active noninverting output (ROUT2B), which allowsapplications using the ring indicator to transmit data while the device is powered down. The device operates atdata signaling rates up to 250 kbit/s and a maximum of 30-V/ms driver output slew rate.
標簽：
MULTICHANNEL
5.5
TO
RS
上傳時間：
2013-10-19
上傳用戶：ddddddd
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Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
標簽：
Virtex
FPGA
PCB
設計手冊
上傳時間：
2014-01-13
上傳用戶：竺羽翎2222
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This application note covers the design considerations of a system using the performance
features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The
design focuses on high system throughput through the AXI Interconnect core with F
MAX
and
area optimizations in certain portions of the design.
The design uses five AXI video direct memory access (VDMA) engines to simultaneously move
10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p
format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video
test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary
video timing signals. Data read by each AXI VDMA is sent to a common on-screen display
(OSD) core capable of multiplexing or overlaying multiple video streams to a single output video
stream. The output of the OSD core drives the DVI video display interface on the board.
Performance monitor blocks are added to capture performance data. All 10 video streams
moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are
controlled by a MicroBlaze™ processor.
The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the
Xilinx® ML605 Rev D evaluation board
標簽：
XAPP
740
AXI
互聯
上傳時間：
2013-11-14
上傳用戶：fdmpy
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Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you
solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce,
distribute, republish, download, display, post, or transmit the Documentation in any form or by any means
including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior
written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation.
Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx
assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections
or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be
provided to you in connection with the Information.
標簽：
CPLD
上傳時間：
2013-10-22
上傳用戶：李哈哈哈
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UART 4 UART參考設計，Xilinx提供VHDL代碼 uart_vhdl
This zip file contains the following folders:
\vhdl_source -- Source VHDL files:
uart.vhd - top level file
txmit.vhd - transmit portion of uart
rcvr.vhd - - receive portion of uart
\vhdl_testfixture -- VHDL Testbench files. This files only include the testbench behavior, they
do not instantiate the DUT. This can easily be done in a top-level VHDL
file or a schematic. This folder contains the following files:
txmit_tb.vhd -- Test bench for txmit.vhd.
rcvr_tf.vhd -- Test bench for rcvr.vhd.
標簽：
UART
Xilinx
VHDL
參考設計
上傳時間：
2013-11-07
上傳用戶：jasson5678
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在研究傳統家用燃氣報警器的基礎上，以ZigBee協議為平臺，構建mesh網狀網絡實現網絡化的智能語音報警系統。由于傳感器本身的溫度和實際環境溫度的影響，傳感器標定后采用軟件補償方法。為了減少系統費用，前端節點采用半功能節點設備，路由器和協調器采用全功能節點設備，構建mesh網絡所形成的家庭內部報警系統，通過通用的電話接口連接到外部的公用電話網絡，啟動語音模塊進行報警。實驗結果表明，在2.4 GHz頻率下傳輸，有墻等障礙物的情況下，節點的傳輸距離大約為35 m，能夠滿足家庭需要，且系統工作穩定，但在功耗方面仍需進一步改善。
Abstract:
On the basis of studying traditional household gas alarm system, this paper proposed the platform for the ZigBee protocol，and constructed mesh network to achieve network-based intelligent voice alarm system. Because of the sensor temperature and the actual environment temperature, this system design used software compensation after calibrating sensor. In order to reduce system cost, semi-functional node devices were used as front-end node, however, full-function devices were used as routers and coordinator，constructed alarm system within the family by building mesh network，connected to the external public telephone network through the common telephone interface, started the voice alarm module. The results indicate that nodes transmit about 35m in the distance in case of walls and other obstacles by 2.4GHz frequency transmission, this is able to meet family needs and work steadily, but still needs further improvement in power consumption.
標簽：
ZigBee
無線智能
家
報警系統
上傳時間：
2013-10-30
上傳用戶：swaylong
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This example provides a description of how to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sends the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must end by '\r'character (keypad ENTER button). Each byte received is retransmitted to theHyperterminal. The string that you have entered is stored in the RxBuffer array. The receivebuffer have a RxBufferSize bytes as maximum.
The USART2 is configured as follow: - BaudRate = 115200 baud - Word Length = 8 Bits - One Stop Bit - No parity - Hardware flow control enabled (RTS and CTS signals) - Receive and transmit enabled - USART Clock disabled - USART CPOL: Clock is active low - USART CPHA: Data is captured on the second edge - USART LastBit: The clock pulse of the last data bit is not output to the SCLK pin
標簽：
V100
STM
100
32V
上傳時間：
2013-10-31
上傳用戶：yy_cn
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Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.
標簽：
Virtex
FPGA
PCB
設計手冊
上傳時間：
2013-11-11
上傳用戶：zwei41
