Implement the step 2 of two-level logic minimization. Our goal is to find the minimum (exact minimum) sum-of-products expression for a given function.
標(biāo)簽： minimization Implement the two-level
上傳時間： 2014-01-09
上傳用戶：無聊來刷下
This file is hysterisis two level controller
標(biāo)簽： controller hysterisis level This
上傳時間： 2014-01-18
上傳用戶：亞亞娟娟123
The W78E58B is an 8-bit microcontroller which has an in-system programmable Flash EPROM for firmware updating. The instruction set of the W78E58B is fully compatible with the standard 8052. The W78E58B contains a 32K bytes of main ROM and a 4K bytes of auxiliary ROM which allows the contents of the 32KB main ROM to be updated by the loader program located at the 4KB auxiliary ROM 512 bytes of on-chip RAM four 8-bit bi-directional and bit-addressable I/O ports an additional 4- bit port P4 three 16-bit timer/counters a serial port. These peripherals are supported by a eight sources two-level interrupt capability. To facilitate programming and verification, the ROM inside the W78E58B allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security
標(biāo)簽： microcontroller programmable in-system W78E58B
上傳時間： 2017-04-27
上傳用戶：yiwen213
Driver to create flat random graphs and two forms of hierarchical graphs (N-level and transit-stub)
標(biāo)簽： graphs hierarchical transit-stu and
上傳時間： 2013-12-20
上傳用戶：ggwz258
基于OFDM的無線寬帶系統(tǒng)仿真It contains mainly two parts, i.e. link-level simulator and system-level simulator. Link-level simulator focus on a single-cell single-user scenario, where signal is transmitted from tx, and estimated at rx. Comparing the difference in tx/rx signal, the error rate can be found out. The output of the link-level simulator is the BLER/BER vs. SNR mapping table, that can be used for the system-level simulation. System-level simulator focus on a multi-cell multi-user scenario. For the sake of simplicity, it takes the mapping table aquired in the link-level simulation, measure the actural SNR, and finds the corresponding error rate.
標(biāo)簽： simulator i.e. system-level link-level
上傳時間： 2016-03-15
上傳用戶：xsnjzljj
this is the best two PDF in frebch level set
標(biāo)簽： frebch level this best
上傳時間： 2013-12-23
上傳用戶：xz85592677
The PCA9517 is a CMOS integrated circuit that provides level shifting between lowvoltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Usingthe PCA9517 enables the system designer to isolate two halves of a bus for both voltageand capacitance. The SDA and SCL pins are over voltage tolerant and arehigh-impedance when the PCA9517 is unpowered.
標(biāo)簽： translating Level 9517 PCA
上傳時間： 2013-12-25
上傳用戶：wsf950131
A program to demonstrate the optimization process of particle swarm optimization. A two-dimensional objective function is visualized by level of grey: the lighter the color, the higher the function value. The particles are shown as red circles, their trajectory as red lines.
標(biāo)簽： optimization two-dimensional demonstrate particle
上傳時間： 2013-12-22
上傳用戶：Andy123456
//Basic packet sending test at the MAC level, used for internal testing only. //This packet test has one node sending out a variety of //differently formatted packets to two assumed destination nodes.
標(biāo)簽： packet test internal sending
上傳時間： 2014-08-21
上傳用戶：CSUSheep
SDRAM 參考設(shè)計:主要包括The following figure shows a high-level block diagram for this reference design followed by a brief description of each sub-section. The design consists of: · PowerPC processor · PLB-OPB bridge · BlockRAM Memory Controller · SDRAM Controller · Two GPIO ports · A UART Port · External SDRAM
標(biāo)簽： high-level following reference diagram
上傳時間： 2013-12-15
上傳用戶：Miyuki
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