The MAX2870 ultra-wideband phase-locked loop (PLL) and voltagecontrol oscillator (VCO) can operate in both integer-N and fractional-Nmodes, similar to the Analog Devices ADF4350 wideband synthesizer.This application note compares the MAX2870 and ADF4350 registers andloop filter design in detail. Users who already familiar with ADF4350 canuse this application note as a quick design reference.
標(biāo)簽： 寄存器 環(huán)路濾波器
上傳時間： 2014-12-23
上傳用戶：變形金剛
Application considerations and circuits for the LT1001 and LT1002 single and dual precision amplifiers are illustrated in a number of circuits, including strain gauge signal conditioners, linearized platinum RTD circuits, an ultra precision dead zone circuit for motor servos and other examples.
上傳時間： 2013-10-18
上傳用戶：dreamboy36
為解決輸油管道溫度壓力參數(shù)實時監(jiān)測的問題，設(shè)計了以C8051F930單片機作為控制核心的超低功耗輸油管道溫度壓力遠(yuǎn)程監(jiān)測系統(tǒng)。現(xiàn)場儀表使用高精度電橋采集數(shù)據(jù)，通過433 MHz短距離無線通信網(wǎng)絡(luò)與遠(yuǎn)程終端RTU進行通信，RTU通過GPRS網(wǎng)絡(luò)與PC上位機進行遠(yuǎn)程數(shù)據(jù)傳輸，在上位機中實現(xiàn)數(shù)據(jù)存儲和圖形化界面顯示，從而實現(xiàn)輸油管道溫度壓力參數(shù)的實時監(jiān)測和異常報警。經(jīng)實驗證明，該系統(tǒng)的12位數(shù)據(jù)采集精度滿足設(shè)計要求，漏碼率小于1%，正常工作時間超過5個月，能實時有效地監(jiān)測輸油管道的溫度壓力參數(shù)，節(jié)省大量人工成本，有效預(yù)防管道參數(shù)異常造成的經(jīng)濟損失和環(huán)境污染。 Abstract: In order to solve the problems on real-time monitoring of pipeline temperature and pressure parameters， the ultra-low power remote pipeline temperature and pressure monitoring system was designed by using the single chip processor C8051F930 as the control core. The high-precision electric bridge was used in field instruments for data collection， the 433MHz short-range wireless communication network was used to make communication between field instrument and RTU， the GPRS was used by the RTU to transmit data to the PC host computer， and the data was stored and displayed in the PC host computer， so the real-time monitoring and exception alerts of pipeline temperature and pressure parameters were achieved. The experiment proves that the system of which error rate is less than 1% over five months working with the 12-bit data acquisition accuracy can effectively monitor the pipeline temperature and pressure parameters in real time， it saves a lot of labor costs and effectively prevents environmental pollution and economic losses caused by abnormal channel parameters.
標(biāo)簽： C8051F930 溫度 壓力 遠(yuǎn)程監(jiān)測系統(tǒng)
上傳時間： 2013-11-07
上傳用戶：cuibaigao
為了在工業(yè)生產(chǎn)及過程控制中準(zhǔn)確測量溫度，設(shè)計了一種基于低功耗MSP430單片機的數(shù)字溫度計。整個系統(tǒng)通過單片機MSP430F1121A控制DS18B20讀取溫度，采用數(shù)碼管顯示，溫度傳感器DS18B20與單片機之間通過串口進行數(shù)據(jù)傳輸。MSP430系列單片機具有超低功耗，且外圍的整合性高，DS18B20只需一個端口即可實現(xiàn)數(shù)據(jù)通信，連接方便。通過多次實驗證明，該系統(tǒng)的測試結(jié)果與實際環(huán)境溫度一致，除了具有接口電路簡單、測量精度高、誤差小、可靠性高等特點外，其低成本、低功耗的特點使其擁有更廣闊的應(yīng)用前景。 Abstract: In order to obtain accurate measuring temperature in industrial production and process control， a digital thermometer based on MSP430 MCU is designed. The system uses MSP430F1121A MCU to control DS18B20， and gets the temperature data， which is displayed on the LED. The temperature sensor DS18B20 and MCU transmit data through serial communication. MSP430 series has ultra-low power and high integration， DS18B20 only needs one port to achieve data communication. Through many experimental results prove， this system is consistent with actual environment temperature. The system has characteristics of interface circuit simple， high measuring accuracy， minor error， high reliability， besides， the characteristics of low cost and low power make it having vaster application prospect.
上傳時間： 2013-10-16
上傳用戶：wettetw
The MSP-FET430U14 is a powerful flash emulation tool to quickly begin application development on the MSP430 MCU. It includes USB debugging interface used to program and debug the MSP430 in-system through the JTAG interface or the pin saving Spy Bi-Wire (2-wire JTAG) protocol. The flash memory can be erased and programmed in seconds with only a few keystrokes, and since the MSP430 flash is ultra-low power, no external power supply is required. The debugging tool interfaces the MSP430 to the included integrated software environment and includes code to start your design immediately. The MSP-FET430UIF development tools supports development with all MSP430 flash devices
上傳時間： 2013-10-28
上傳用戶：13691535575
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時間： 2013-11-13
上傳用戶：瓦力瓦力hong
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時間： 2013-11-21
上傳用戶：wxqman
本系統(tǒng)是在asp版《在線文件管理器》的基礎(chǔ)上設(shè)計制作，取其精華，棄其糟粕，功能更強，效率更高，具有以下特點： 1。采用三層結(jié)構(gòu)開發(fā)，程序邏輯和用戶界面徹底分離，可輕松換膚。 2。全部代碼采用Ultra Edit編寫，不使用任何可視化開發(fā)工具，精確控制代碼流程，確保代碼高效率運行。 3。自行開發(fā)自定義控件，不產(chǎn)生任何一丁點的HTML代碼冗余。 4。盡可能的減少客戶與服務(wù)器的交互，降低對服務(wù)器資源消耗，減少網(wǎng)絡(luò)傳輸。 5。真正多用戶系統(tǒng)，可分別為每個用戶設(shè)置可管理的文件類型，目錄等，上傳的單個文件大小限制等。 6。各用戶環(huán)境自由配置，風(fēng)格自選（如果有多個風(fēng)格的話），可自由設(shè)置每頁顯示的文件及目錄數(shù)等。 7。文件與目錄翻頁分開，即使管理同一目錄下的數(shù)萬個文件也不再出現(xiàn)程序超時現(xiàn)象。 8。功能強大，除了asp版具備的全部功能如上傳、下載、編輯、批量復(fù)制、移動、粘貼外還具備文件快速過濾搜索，智能修改文件屬性。 9。效率極高。經(jīng)測試，在一太普通PC上對一個包含50000個文件的目錄進行瀏覽管理，任意翻頁，執(zhí)行時間均不超過1秒。過濾或者搜索則更是低至僅0.3秒的執(zhí)行時間。而windows資源管理器打開目錄或者asp版翻至最后一頁都需要6.5秒甚至更長時間。
上傳時間： 2015-04-01
上傳用戶：kr770906
本系統(tǒng)是在asp版《在線文件管理器》的基礎(chǔ)上設(shè)計制作，取其精華，棄其糟粕，功能更強，效率更高，具有以下特點： 1。采用三層結(jié)構(gòu)開發(fā)，程序邏輯和用戶界面徹底分離，可輕松換膚。 2。全部代碼采用Ultra Edit編寫，不使用任何可視化開發(fā)工具，精確控制代碼流程，確保代碼高效率運行。 3。自行開發(fā)自定義控件，不產(chǎn)生任何一丁點的HTML代碼冗余。 4。盡可能的減少客戶與服務(wù)器的交互，降低對服務(wù)器資源消耗，減少網(wǎng)絡(luò)傳輸。 5。真正多用戶系統(tǒng)，可分別為每個用戶設(shè)置可管理的文件類型，目錄等，上傳的單個文件大小限制等。 6。各用戶環(huán)境自由配置，風(fēng)格自選（如果有多個風(fēng)格的話），可自由設(shè)置每頁顯示的文件及目錄數(shù)等。 7。文件與目錄翻頁分開，即使管理同一目錄下的數(shù)萬個文件也不再出現(xiàn)程序超時現(xiàn)象。 8。功能強大，除了asp版具備的全部功能如上傳、下載、編輯、批量復(fù)制、移動、粘貼外還具備文件快速過濾搜索，智能修改文件屬性。 9。效率極高。經(jīng)測試，在一太普通PC上對一個包含50000個文件的目錄進行瀏覽管理，任意翻頁，執(zhí)行時間均不超過1秒。過濾或者搜索則更是低至僅0.3秒的執(zhí)行時間。而windows資源管理器打開目錄或者asp版翻至最后一頁都需要6.5秒甚至更長時間。
上傳時間： 2014-01-05
上傳用戶：冇尾飛鉈
Squaring circuits are an important building block for impulse-radio UWB non-coherent receivers. This work proposes a squarer, based on the quadratic law of saturated transistors. Such a circuit has already been proposed for lower frequency applications, therefore this work focuses on the extension to ultra wide bandwidth, with particular care to the consequences related to the deviation from the ideal quadratic law of 0.18μm CMOS transistors.
標(biāo)簽： impulse-radio non-coherent important receivers
上傳時間： 2013-12-24
上傳用戶：kikye
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