The purpose of this book is to present detailed fundamental information on a global positioning system (GPS) receiver. Although GPS receivers are popu- larly used in every-day life, their operation principles cannot be easily found in one book. Most other types of receivers process the input signals to obtain the necessary information easily, such as in amplitude modulation (AM) and frequency modulation (FM) radios. In a GPS receiver the signal is processed to obtain the required information, which in turn is used to calculate the user position. Therefore, at least two areas of discipline, receiver technology and navigation scheme, are employed in a GPS receiver. This book covers both areas.
標簽： Fundamentals_of_Global_Positionin g_System_Receivers
上傳時間： 2020-06-09
上傳用戶：shancjb
If one examines the current literature on GPS receiver design, most of it is quite a bit above the level of the novice. It is taken for granted that the reader is already at a fairly high level of understanding and proceeds from there. This text will be an attempt to take the reader through the concepts and circuits needed to be able to understand how a GPS receiver works from the antenna to the solution of user position.
標簽： Fundamentals_of_Global_Positionin g_System
上傳時間： 2020-06-09
上傳用戶：shancjb
Of the various applications that satellites have been used for, one of the most promising is that of global positioning. Made possible by Global Navigation Satellite Systems, global positioning enables any user to know his or her exact position on Earth. Nowadays, the only fully functioning system is the American Global Positioning System (GPS). However, the European system, known as Galileo, is expected to be operative in 2012.
上傳時間： 2020-06-09
上傳用戶：shancjb
EES_REFPROP源碼，User Instructions for EES_REFPROP
上傳時間： 2021-08-24
上傳用戶：18868103493
FPGA讀寫SD卡讀取BMP圖片通過LCD顯示例程實驗 Verilog邏輯源碼Quartus工程文件+文檔說明,FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 實驗簡介在前面的實驗中我們練習了 SD 卡讀寫，VGA 視頻顯示等例程，本實驗將 SD 卡里的 BMP 圖片讀出，寫入到外部存儲器，再通過 VGA、LCD 等顯示。本實驗如果通過液晶屏顯示，需要有液晶屏模塊。2 實驗原理在前面的實驗中我們在 VGA、LCD 上顯示的是彩條，是 FPGA 內(nèi)部產(chǎn)生的數(shù)據(jù)，本實驗將彩條替換為 SD 內(nèi)的 BMP 圖片數(shù)據(jù)，但是 SD 卡讀取速度遠遠不能滿足顯示速度的要求，只能先寫入外部高速 RAM，再讀出后給視頻時序模塊顯示module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24
標簽： fpga
上傳時間： 2021-10-27
上傳用戶：
MSP430f249單片機文檔資料+軟件DEMO程序50例程合集:MSP430f249 用戶手冊.pdfmsp430x24x_1msp430x24x_1_vlomsp430x24x_adc12_01msp430x24x_adc12_02msp430x24x_adc12_03msp430x24x_clksmsp430x24x_compA_01msp430x24x_compA_02msp430x24x_compA_04msp430x24x_compA_05msp430x24x_dco_flashcalmsp430x24x_flashwrite_01msp430x24x_flashwrite_02msp430x24x_flashwrite_03msp430x24x_fll_01msp430x24x_fll_02msp430x24x_hfxt2msp430x24x_hfxt2_nmimsp430x24x_lpm3msp430x24x_lpm3_vlomsp430x24x_MPY_01msp430x24x_MPY_02msp430x24x_nmimsp430x24x_OF_LFXT1msp430x24x_OF_XT2msp430x24x_P1_01msp430x24x_P1_02msp430x24x_P1_05msp430x24x_roscmsp430x24x_svs_01msp430x24x_ta_01msp430x24x_ta_02msp430x24x_tb_10msp430x24x_uscia0_irda_01msp430x24x_uscia0_irda_02msp430x24x_uscia0_irda_03msp430x24x_uscia0_spi_01msp430x24x_uscia0_uart_01_115kmsp430x24x_uscia0_uart_01_115k_lpmmsp430x24x_uscia0_uart_01_19200msp430x24x_uscia0_uart_01_9600msp430x24x_uscia0_uart_04_9600msp430x24x_uscia0_uart_05_9600msp430x24x_uscia0_uart_06_9600msp430x24x_uscia0_uart_07_9600msp430x24x_uscia0_uart_08_9600msp430x24x_uscia1_irda_01msp430x24x_uscia1_spi_09msp430x24x_uscia1_spi_10msp430x24x_uscia1_uart_05_9600msp430x24x_uscib0_i2c_01msp430x24x_uscib0_i2c_02msp430x24x_uscib0_i2c_04msp430x24x_uscib0_i2c_05msp430x24x_uscib0_i2c_06msp430x24x_uscib0_i2c_07msp430x24x_uscib0_i2c_08msp430x24x_uscib0_i2c_09msp430x24x_uscib0_i2c_10msp430x24x_uscib0_i2c_11msp430x24x_uscib0_i2c_15msp430x24x_uscib0_spi_01msp430x24x_uscib0_spi_02msp430x24x_uscib0_spi_09msp430x24x_uscib0_spi_10msp430x24x_uscib1_i2c_06msp430x24x_uscib1_i2c_07msp430x24x_uscib1_spi_09msp430x24x_uscib1_spi_10msp430x24x_wdt_01msp430x24x_wdt_02msp430x24x_wdt_04msp430x24x_wdt_05msp430x24x_wdt_06MSP430x2xx Family User's Guide.pdf
標簽： msp430f249 單片機
上傳時間： 2021-11-03
上傳用戶：
IIC接口E2PROM(AT24C64) 讀寫VERILOG 驅(qū)動源碼+仿真激勵文件:module i2c_dri #( parameter SLAVE_ADDR = 7'b1010000 , //EEPROM從機地址 parameter CLK_FREQ = 26'd50_000_000, //模塊輸入的時鐘頻率 parameter I2C_FREQ = 18'd250_000 //IIC_SCL的時鐘頻率 ) ( input clk , input rst_n , //i2c interface input i2c_exec , //I2C觸發(fā)執(zhí)行信號 input bit_ctrl , //字地址位控制(16b/8b) input i2c_rh_wl , //I2C讀寫控制信號 input [15:0] i2c_addr , //I2C器件內(nèi)地址 input [ 7:0] i2c_data_w , //I2C要寫的數(shù)據(jù) output reg [ 7:0] i2c_data_r , //I2C讀出的數(shù)據(jù) output reg i2c_done , //I2C一次操作完成 output reg i2c_ack , //I2C應答標志 0:應答 1:未應答 output reg scl , //I2C的SCL時鐘信號 inout sda , //I2C的SDA信號 //user interface output reg dri_clk //驅(qū)動I2C操作的驅(qū)動時鐘 );//localparam definelocalparam st_idle = 8'b0000_0001; //空閑狀態(tài)localparam st_sladdr = 8'b0000_0010; //發(fā)送器件地址(slave address)localparam st_addr16 = 8'b0000_0100; //發(fā)送16位字地址localparam st_addr8 = 8'b0000_1000; //發(fā)送8位字地址localparam st_data_wr = 8'b0001_0000; //寫數(shù)據(jù)(8 bit)localparam st_addr_rd = 8'b0010_0000; //發(fā)送器件地址讀localparam st_data_rd = 8'b0100_0000; //讀數(shù)據(jù)(8 bit)localparam st_stop = 8'b1000_0000; //結(jié)束I2C操作//reg definereg sda_dir ; //I2C數(shù)據(jù)(SDA)方向控制reg sda_out ; //SDA輸出信號reg st_done ; //狀態(tài)結(jié)束reg wr_flag ; //寫標志reg [ 6:0] cnt ; //計數(shù)reg [ 7:0] cur_state ; //狀態(tài)機當前狀態(tài)reg [ 7:0] next_state; //狀態(tài)機下一狀態(tài)reg [15:0] addr_t ; //地址reg [ 7:0] data_r ; //讀取的數(shù)據(jù)reg [ 7:0] data_wr_t ; //I2C需寫的數(shù)據(jù)的臨時寄存reg [ 9:0] clk_cnt ; //分頻時
標簽： iic 接口 e2prom at24c64 verilog 驅(qū)動 仿真
上傳時間： 2021-11-05
上傳用戶：
全志A33芯片資料A33核心板技術(shù)手冊硬件參考設計A33開發(fā)板CADENCE原理圖PADS PCB圖文件：A33 brief 20140522.pdfA33 Datasheet release1.0.pdfA33 user manual release 1.0.pdfA33-Core3引腳定義表.pdfA33-Core3核心板外圍電路設計參考.pdfA33-Core3核心板硬件手冊.pdfA33_Vstar3使用手冊VerC.pdf尺寸圖底板PCB圖開發(fā)底板原理圖PCB網(wǎng)卡電路參考設計說明.txtA33-Core3引腳圖.pdfA33-Vstar-LCD07-10.pdfRER-A33-DVK3-padslogic95.schRER-A33-DVK3-SCH.DSNRER-A33-DVK3-SCH.pdf第二版改MIPI座子
上傳時間： 2021-11-08
上傳用戶：qdxqdxqdxqdx
基于FPGA設計的sdram讀寫測試實驗Verilog邏輯源碼Quartus工程文件+文檔說明，DRAM選用海力士公司的 HY57V2562 型號,容量為的 256Mbit,采用了 54 引腳的TSOP 封裝, 數(shù)據(jù)寬度都為 16 位, 工作電壓為 3.3V,并丏采用同步接口方式所有的信號都是時鐘信號。FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
標簽： fpga sdram verilog quartus
上傳時間： 2021-12-18
上傳用戶：
Xilinx FPGA Virtex-7 全系列（AD集成封裝庫），IntLib后綴文件，PCB封裝帶3D視圖，拆分后文件為PcbLib+SchLib格式，Altium Designer原理圖庫+PCB封裝庫，集成封裝型號列表：Library Component Count : 157Name Description----------------------------------------------------------------------------------------------------XC7V2000T-1FHG1761C Virtex-7 FPGA, 1200 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 1, Commerical Grade, Pb-FreeXC7V2000T-1FHG1761I Virtex-7 FPGA, 1200 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7V2000T-1FLG1925C Virtex-7 FPGA, 1200 User I/Os, 16 GTX, 1924-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7V2000T-1FLG1925I Virtex-7 FPGA, 1200 User I/Os, 16 GTX, 1924-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7V2000T-2FHG1761C Virtex-7 FPGA, 1200 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 2, Commerical Grade, Pb-FreeXC7V2000T-2FLG1925C Virtex-7 FPGA, 1200 User I/Os, 16 GTX, 1924-Ball BGA, Speed Grade 2, Commercial Grade, Pb-FreeXC7V2000T-2GFHG1761EVirtex-7 FPGA, 1200 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 2G, Extended Grade, Pb-FreeXC7V2000T-2GFLG1925EVirtex-7 FPGA, 1200 User I/Os, 16 GTX, 1924-Ball BGA, Speed Grade 2G, Extended Grade, Pb-FreeXC7V2000T-2LFHG1761EVirtex-7 FPGA, 1200 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 2L, Extended Grade, Pb-FreeXC7V2000T-2LFLG1925EVirtex-7 FPGA, 1200 User I/Os, 16 GTX, 1924-Ball BGA, Speed Grade 2L, Extended Grade, Pb-FreeXC7V585T-1FFG1157C Virtex-7 FPGA, 850 User I/Os, 20 GTX, 1156-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7V585T-1FFG1157I Virtex-7 FPGA, 850 User I/Os, 20 GTX, 1156-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7V585T-1FFG1761C Virtex-7 FPGA, 850 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 1, Commercial Grade, Pb-FreeXC7V585T-1FFG1761I Virtex-7 FPGA, 850 User I/Os, 36 GTX, 1760-Ball BGA, Speed Grade 1, Industrial Grade, Pb-FreeXC7V585T-2FFG1157C Virtex-7 FPGA, 850 User I/Os, 20 GTX, 1156-Ball BGA, Speed Grade 2, Commercial Grade, Pb-FreeXC7V
上傳時間： 2021-12-22
上傳用戶：aben
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