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wHILE

wHILE是計算機的一種基本循環(huán)模式。當滿足條件時進入循環(huán),進入循環(huán)后,當條件不滿足時,跳出循環(huán)。wHILE語句的一般表達式為:wHILE(表達式){循環(huán)體}。
  • 6小時學(xué)會labview

    6小時學(xué)會labview, labview Six Hour Course – Instructor Notes   This zip file contains material designed to give students a working knowledge of labview in a 6 hour timeframe. The contents are: Instructor Notes.doc – this document. labviewIntroduction-SixHour.ppt – a PowerPoint presentation containing screenshots and notes on the topics covered by the course. Convert C to F (Ex1).vi – Exercise 1 solution VI. Convert C to F (Ex2).vi – Exercise 2 solution subVI. Thermometer-DAQ (Ex2).vi – Exercise 2 solution VI. Temperature Monitor (Ex3).vi – Exercise 3 solution VI. Thermometer (Ex4).vi – Exercise 4 solution subVI. Convert C to F (Ex4).vi – Exercise 4 solution subVI. Temperature Logger (Ex4).vi – Exercise 4 solution VI. Multiplot Graph (Ex5).vi – Exercise 5 solution VI. Square Root (Ex6).vi – Exercise 6 solution VI. State Machine 1 (Ex7).vi – Exercise 7 solution VI.   The slides can be presented in two three hour labs, or six one hour lectures. Depending on the time and resources available in class, you can choose whether to assign the exercises as homework or to be done in class. If you decide to assign the exercises in class, it is best to assign them in order with the presentation. This way the students can create VI’s wHILE the relevant information is still fresh. The notes associated with the exercise slide should be sufficient to guide the students to a solution. The solution files included are one possible solution, but by no means the only solution.

    標簽: labview

    上傳時間: 2013-10-13

    上傳用戶:zjwangyichao

  • 克服了正交頻分復(fù)用(OFDM)和IEEE 1901.2智能電網(wǎng)通信的挑戰(zhàn)

    Abstract: wHILE many questions still surround the creation and deployment of the smart grid, the need for a reliablecommunications infrastructure is indisputable. Developers of the IEEE 1901.2 standard identified difficult channel conditionscharacteristic of low-frequency powerline communications and implemented an orthogonal frequency division multiplexing (OFDM)architecture using advanced modulation and channel-coding techniques. This strategy helped to ensure a robust communicationsnetwork for the smart grid.

    標簽: 1901.2 OFDM IEEE 正交頻分復(fù)用

    上傳時間: 2013-10-18

    上傳用戶:myworkpost

  • MAX7060的ASK_FSK的ISM射頻發(fā)射機

    Abstract: This application note illustrates the flexibility of the MAX7060 ASK/FSK transmitter. wHILE the currently available evaluationkit (EV kit) has been optimized for the device's use in a specific frequency band (i.e., 288MHz to 390MHz), this document addresseshow the EV kit circuitry can be modified for improved operation at 433.92MHz, a frequency commonly used in Europe. Twoalternative match and filter configurations are presented: one for optimizing drain efficiency, the other for achieving higher transmitpower. Features and capabilities of earlier Maxim industrial, scientific, and medical radio-frequency (ISM-RF) transmitters areprovided, allowing comparison of the MAX7060 to its predecessors. Several design guidelines and cautions for using the MAX7060are discussed.

    標簽: ASK_FSK 7060 MAX ISM

    上傳時間: 2013-11-14

    上傳用戶:swaylong

  • S參數(shù)的設(shè)計與應(yīng)用

    Agilent AN 154 S-Parameter Design Application Note S參數(shù)的設(shè)計與應(yīng)用 The need for new high-frequency, solid-state circuitdesign techniques has been recognized both by microwaveengineers and circuit designers. These engineersare being asked to design solid state circuitsthat will operate at higher and higher frequencies.The development of microwave transistors andAgilent Technologies’ network analysis instrumentationsystems that permit complete network characterizationin the microwave frequency rangehave greatly assisted these engineers in their work.The Agilent Microwave Division’s lab staff hasdeveloped a high frequency circuit design seminarto assist their counterparts in R&D labs throughoutthe world. This seminar has been presentedin a number of locations in the United States andEurope.From the experience gained in presenting this originalseminar, we have developed a four-part videotape, S-Parameter Design Seminar. wHILE the technologyof high frequency circuit design is everchanging, the concepts upon which this technologyhas been built are relatively invariant.The content of the S-Parameter Design Seminar isas follows:

    標簽: S參數(shù)

    上傳時間: 2013-12-19

    上傳用戶:aa54

  • Algorithms(算法概論)pdf

    This book evolved over the past ten years from a set of lecture notes developed wHILE teaching the undergraduate Algorithms course at Berkeley and U.C. San Diego. Our way of teaching this course evolved tremendously over these years in a number of directions, partly to address our students' background (undeveloped formal skills outside of programming), and partly to reect the maturing of the eld in general, as we have come to see it. The notes increasingly crystallized into a narrative, and we progressively structured the course to emphasize the ?story line? implicit in the progression of the material. As a result, the topics were carefully selected and clustered. No attempt was made to be encyclopedic, and this freed us to include topics traditionally de-emphasized or omitted from most Algorithms books.

    標簽: Algorithms 算法

    上傳時間: 2013-11-11

    上傳用戶:JamesB

  • 飛思卡爾智能車的舵機測試程序

    飛思卡爾智能車的舵機測試程序 #include <hidef.h>      /* common defines and macros */#include <MC9S12XS128.h>     /* derivative information */#pragma LINK_INFO DERIVATIVE "mc9s12xs128" void SetBusCLK_16M(void)             {       CLKSEL=0X00;        PLLCTL_PLLON=1;          //鎖相環(huán)電路允許位    SYNR=0x00 | 0x01;        //SYNR=1    REFDV=0x80 | 0x01;          POSTDIV=0x00;            _asm(nop);              _asm(nop);    wHILE(!(CRGFLG_LOCK==1));       CLKSEL_PLLSEL =1;          } void PWM_01(void) {     //舵機初始化   PWMCTL_CON01=1;    //0和1聯(lián)合成16位PWM;    PWMCAE_CAE1=0;    //選擇輸出模式為左對齊輸出模式    PWMCNT01 = 0;     //計數(shù)器清零;    PWMPOL_PPOL1=1;    //先輸出高電平,計數(shù)到DTY時,反轉(zhuǎn)電平    PWMPRCLK = 0X40;    //clockA 不分頻,clockA=busclock=16MHz;CLK B 16分頻:1Mhz     PWMSCLA = 0x08;    //對clock SA 16分頻,pwm clock=clockA/16=1MHz;         PWMCLK_PCLK1 = 1;   //選擇clock SA做時鐘源    PWMPER01 = 20000;   //周期20ms; 50Hz;    PWMDTY01 = 1500;   //高電平時間為1.5ms;     PWME_PWME1 = 1;   

    標簽: 飛思卡爾智能車 舵機 測試程序

    上傳時間: 2013-11-04

    上傳用戶:狗日的日子

  • C語言基礎(chǔ)教材

    目錄 C語言基礎(chǔ)知識  C 語言簡介  C 語言的特點…  C 語言的發(fā)展和標準化…數(shù)據(jù)類型、運算、表達式和編譯預(yù)處理  數(shù)據(jù)類型…  基本類型與數(shù)據(jù)表示  整數(shù)類型和整數(shù)的表示…  實數(shù)類型和實數(shù)的表示…  字符類型和字符的表示…  運算符、表達式與計算…  算術(shù)運算符  算術(shù)表達式  表達式的求值…  變量——概念、定義和使用…  變量的定義0  變量的使用:取值與賦值  預(yù)處理  文件包含命令…  宏定義與宏替換…邏輯判斷與運算…   關(guān)系運算和邏輯運算  復(fù)雜條件的描述0  i f語句循環(huán)控制  whi le語句  for語句…  循環(huán)程序常用的若干機制  增量和減量運算符(++、--)  逗號運算符  控制結(jié)構(gòu)和控制語句  do-wHILE循環(huán)結(jié)構(gòu)…  流程控制語句…  goto語句…  開關(guān)語句…函數(shù)  概述…  函數(shù)定義和程序的函數(shù)分解…  函數(shù)定義…  函數(shù)調(diào)用…數(shù)組  數(shù)組的概念、定義和使用  數(shù)組變量定義…  數(shù)組的使用  數(shù)組的初始化…結(jié)構(gòu)  結(jié)構(gòu)(struct)  結(jié)構(gòu)說明與變量定義  結(jié)構(gòu)變量的初始化和使用  結(jié)構(gòu)與函數(shù)  處理結(jié)構(gòu)的函數(shù)0指針  指針的概念  指針操作…  指針作為函數(shù)的參數(shù)  與指針有關(guān)的一些問題…  指針與數(shù)組  指向數(shù)組元素的指針  基于指針運算的數(shù)組程序設(shè)計  數(shù)組參數(shù)與指針  字符指針與字符數(shù)組0

    標簽: C語言 教材

    上傳時間: 2013-11-16

    上傳用戶:asdkin

  • c8051f330 C程序源代碼

    //------------------------------------------------------------------------------------//此程序為ADC轉(zhuǎn)換程序,可以選擇向ADC0BUSY寫1或用定時器0,1,2,3作為ADC的啟動信號。////------------------------------------------------------------------------------------//頭文件定義//------------------------------------------------------------------------------------//#include <c8051f330.h>               #include <stdio.h> //-----------------------------------------------------------------------------// 定義16位特殊功能寄存器//----------------------------------------------------------------------------- sfr16 ADC0     = 0xbd;                sfr16 TMR0RL   = 0xca;                                                                                               sfr16 TMR1RL   = 0xca;                 sfr16 TMR2RL   =0xca;                 sfr16 TMR3RL   =0xca;               sfr16 TMR0     = 0xCC;              sfr16 TMR1     = 0xCC;                sfr16 TMR2     = 0xcc;               sfr16 TMR3     = 0xcc;               //-----------------------------------------------------------------------------// 全局變量定義//-----------------------------------------------------------------------------char i;int result;                       //-----------------------------------------------------------------------------//定義常量//-----------------------------------------------------------------------------#define SYSCLK       49000000        #define SAMPLE_RATE  50000             //------------------------------------------------------------------------------------// 定義函數(shù)//------------------------------------------------------------------------------------void SYSCLK_Init (void);void PORT_Init (void);void Timer0_Init (int counts);void Timer1_Init (int counts);void Timer2_Init (int counts);void Timer3_Init (int counts);void ADC0_Init(void);void ADC0_ISR (void);void ADC0_CNVS_ADC0h(void);//------------------------------------------------------------------------------------// 主程序//------------------------------------------------------------------------------------ void main (void) {       int ADCRESULT[50] ;  int k;                     PCA0MD &= ~0x40;                       // 禁止看門狗                   SYSCLK_Init ();                        PORT_Init ();    Timer0_Init (SYSCLK/SAMPLE_RATE);     //Timer1_Init (SYSCLK/SAMPLE_RATE);     //選擇相應(yīng)的啟動方式   //Timer2_Init (SYSCLK/SAMPLE_RATE);    //Timer3_Init (SYSCLK/SAMPLE_RATE);          ADC0_Init();   EA=1;   wHILE(1)            {     //ADC0_CNVS_ADC0h();  k=ADC0;    ADCRESULT[i]=result;                   //此處設(shè)斷點,觀察ADCRESULT的結(jié)果          }   }

    標簽: c8051f330 C程序 源代碼

    上傳時間: 2013-10-13

    上傳用戶:SimonQQ

  • 溫濕度傳感器 sht11 仿真程序下載

    溫濕度傳感器 sht11 仿真程序 sbit out =P3^0; //加熱口  //sbit input =P1^1;//檢測口  //sbit speek =P2^0;//報警  sbit clo =P3^7;//時鐘  sbit ST =P3^5;//開始  sbit EOC =P3^6;//成功信號  sbit gwei =P3^4;//個位  sbit swei =P3^3;//十位 sbit bwei =P3^2;//百位 sbit qwei =P3^1;//千位 sbit speak =P0^0;//報警音 sbit bjled =P0^1;//報警燈 sbit zcled =P0^2;//正常LED  int count;  uchar xianzhi;//取轉(zhuǎn)換結(jié)果 uchar seth;//高時間 uchar setl;//低時間 uchar seth_mi;//高時間 uchar setl_mi;//低時間  bit  hlbz;//高低標志  bit  clbz;  bit  spbz;       ///定時中斷程序/// void t0 (void) interrupt 1 using 0 {     TH0=(65536-200)/256;//5ms*200=1000ms=1s   TL0=(65536-200)%256;  clo=!clo;//產(chǎn)生時鐘      if(count>5000)   {     if(hlbz)            {       if(seth_mi==0){seth_mi=seth;hlbz=0;out=0;}    else seth_mi--;       }     if(!hlbz)            {       if(setl_mi==0){setl_mi=setl;hlbz=1;out=1;}    else setl_mi--;       }   count=0;   }      else count++;         } ///////////// ///////延時/////// delay(int i) {    wHILE(--i);          }     ///////顯示處理/////// xianshi() {      int   abcd=0;     int i;     for (i=0;i<5;i++) {   abcd=xianzhi;  gwei=1;  swei=1;  bwei=1;  qwei=1;  P1=dispcode[abcd/1000];   qwei=0;  delay(70);   qwei=1;  abcd=abcd%1000;  P1=dispcode[abcd/100];  bwei=0;  delay(70);  bwei=1;   abcd=abcd%100;  P1=dispcode[abcd/10];  swei=0;  delay(70);  swei=1;  abcd=abcd%10;  P1=dispcode[abcd];  gwei=0;  delay(70);  gwei=1;  } }   doing()   {     if(xianzhi>100)     {bjled=0;speak=1;zcled=1;}  else {bjled=1;speak=0;zcled=0;}   }   void main(void)  {  seth=60;//h60秒  setl=90;//l90秒  seth_mi=60;//h60秒  setl_mi=90;//l90秒  TMOD=0X01;//定時0 16位工作模式   TH0=(65536-200)/256;   TL0=(65536-200)%256;    TR0=1; //開始計時  ET0=1;   //開定時0中斷  EA=1;    //開全中斷  wHILE(1)  {      ST=0;    _nop_();     ST=1;    _nop_();     ST=0;  //   EOC=0;          xianshi();       wHILE(!EOC)   {         xianshi();    }        xianzhi=P2;             xianshi();     doing();  }  }

    標簽: sht 11 溫濕度傳感器 仿真程序

    上傳時間: 2013-11-07

    上傳用戶:我們的船長

  • Xilinx UltraScale:新一代架構(gòu)滿足您的新一代架構(gòu)需求(EN)

      中文版詳情瀏覽:http://www.elecfans.com/emb/fpga/20130715324029.html   Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture    The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.   The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity wHILE intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.   Some of the UltraScale architecture breakthroughs include:   • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%    • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability   • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization   • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard    • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets   • Greatly enhanced DSP and packet handling   The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.

    標簽: UltraScale Xilinx 架構(gòu)

    上傳時間: 2013-11-21

    上傳用戶:wxqman

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