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  • ABAQUS is a general purpose finite element analysis program which is widely used to analyses mechani

    ABAQUS is a general purpose finite element analysis program which is widely used to analyses mechanical, structure and civil engineering problems. Abaqus has some special feature for analysing fracture mechanics problems, and therefore it is a main tools for the FE-analysis in the Fracture Group at the Mechanical Engineering at Glasgow Universtity. The software which can transfer data from Abaqus into a Matlab readable environment has been developed as a part of a research program in Constraint Estimation in Fracture Mechanics. This research program was funded by a grant from the Defence Research Agency through Prof. J. Sumpter.

    標(biāo)簽: analysis analyses general element

    上傳時(shí)間: 2015-05-13

    上傳用戶:xfbs821

  • GUI Ant-Miner is a tool for extracting classification rules from data. It is an updated version of a

    GUI Ant-Miner is a tool for extracting classification rules from data. It is an updated version of a data mining algorithm called Ant-Miner (Ant Colony-based Data Miner), which was proposed in 2002 by Parpinelli, Lopes and Freitas.

    標(biāo)簽: classification extracting Ant-Miner updated

    上傳時(shí)間: 2015-05-13

    上傳用戶:ainimao

  • 很好的linux內(nèi)核調(diào)試軟件 兼轅馬

    很好的linux內(nèi)核調(diào)試軟件 兼轅馬,沒(méi)有密碼。 The ia64 and ix86 directories contain versions of kdb prior to v2.0 (kdb version v2.0, not the kernel version). Older versions of kdb had complete patches for each architecture it supported, each patch included all the common kdb code. This format was awkward to maintain and use for multiple platforms. Starting with kdb v2.0 there is a common patch against each kernel which contains all the architecture independent code plus separate architecture dependent patches. Either use an old style (v1.8 or v1.9) kdb patch or use a new style (v2.0) common patch plus the corresponding architecture dependent patch.

    標(biāo)簽: linux 內(nèi)核 調(diào)試軟件

    上傳時(shí)間: 2014-01-21

    上傳用戶:wyc199288

  • Title: STL Tutorial and Reference Guide: C++ Programming with the Standard Template Library (2nd Edi

    Title: STL Tutorial and Reference Guide: C++ Programming with the Standard Template Library (2nd Edition) Author: David R. Musser / Gillmer J. Derge / Atul Saini / Gilmer J. Derge Publisher: Addison-Wesley Page: 560 Edition: 2nd edition (March 27, 2001) Format: PDF Summary: The Standard Template Library was created as the first library of genetic algorithms and data structures, with four ideas in mind: generic programming, abstractness without loss of efficiency, the Von Neumann computation model, and value semantics. This guide provides a tutorial, a description of each element of the library, and sample applications. The expanded second edition includes new code examples and demonstrations of the use of STL in real-world C++ software development it reflects changes made to STL for the final ANSI/ISO C++ language standard.

    標(biāo)簽: Programming Reference Standard Template

    上傳時(shí)間: 2014-01-19

    上傳用戶:netwolf

  • Welcome to PMOS. PMOS is a set of modules, mostly written in Modula-2, to support multitasking. PMO

    Welcome to PMOS. PMOS is a set of modules, mostly written in Modula-2, to support multitasking. PMOS was designed primarily with real-time applications in mind. It is not an operating system in the conventional sense rather, it is a collection of modules which you can import into your own programs, and which in particular allow you to write multi-threaded programs.

    標(biāo)簽: PMOS multitasking Welcome modules

    上傳時(shí)間: 2015-07-10

    上傳用戶:windwolf2000

  • county, random population coordinates were generated using the complete spatial randomness (CSR) fun

    county, random population coordinates were generated using the complete spatial randomness (CSR) function in S-PLUS. Then, the background information was attached to each individual county based on the county?s distribution for the class of interest. Finally, all counties were merged into a single dataset that describes the whole state

    標(biāo)簽: coordinates population randomness generated

    上傳時(shí)間: 2014-01-18

    上傳用戶:hn891122

  • MySQL 5.1參考手冊(cè) 這是MySQL參考手冊(cè)的翻譯版本

    MySQL 5.1參考手冊(cè) 這是MySQL參考手冊(cè)的翻譯版本,關(guān)于MySQL參考手冊(cè),請(qǐng)?jiān)L問(wèn)dev.mysql.com。 原始參考手冊(cè)為英文版。 This translation was done by MySQL partner GreatLinux, Beijing, People s Republic of China. GreatLinux Inc. 北京萬(wàn)里開(kāi)源軟件有限公司在全國(guó)范圍提供MySQL產(chǎn)品相關(guān)的商務(wù)及 技術(shù)方面的咨詢與支持服務(wù)。垂詢請(qǐng)致電:8610-65694500,或發(fā)送郵件至:sales@greatlinux.com.

    標(biāo)簽: MySQL 5.1 參考手冊(cè) 翻譯

    上傳時(shí)間: 2015-07-17

    上傳用戶:qq21508895

  • As of UnZip 5.42, this source has been removed from Info-ZIP s UnZip source distribution because of

    As of UnZip 5.42, this source has been removed from Info-ZIP s UnZip source distribution because of its conflicting copyright. There are no plans to ever rewrite this code from scratch, because the unreduce algorithm was never used in the "real" world.

    標(biāo)簽: source UnZip distribution Info-ZIP

    上傳時(shí)間: 2013-12-19

    上傳用戶:songrui

  • Designing the mode mini manual provided the software design of 23 kinds of typical models mode, the

    Designing the mode mini manual provided the software design of 23 kinds of typical models mode, the in aid of procedure member was better to develop procedure.

    標(biāo)簽: the mode Designing provided

    上傳時(shí)間: 2014-01-19

    上傳用戶:bruce5996

  • 關(guān)于FPGA流水線設(shè)計(jì)的論文 This work investigates the use of very deep pipelines for implementing circuits in

    關(guān)于FPGA流水線設(shè)計(jì)的論文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.

    標(biāo)簽: investigates implementing pipelines circuits

    上傳時(shí)間: 2015-07-26

    上傳用戶:CHINA526

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