The PCA9517 is a CMOS integrated circuit that provides level shifting between lowvoltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications.while retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Usingthe PCA9517 enables the system designer to isolate two halves of a bus for both voltageand capacitance. The SDA and SCL pins are over voltage tolerant and arehigh-impedance when the PCA9517 is unpowered.
標(biāo)簽： translating Level 9517 PCA
上傳時(shí)間： 2013-12-25
上傳用戶：wsf950131
The PCA9518 is a BiCMOS integrated circuit intended forapplication in I2C and SMBus systems.while retaining all the operating modes and features of the I2Csystem, it permits extension of the I2C-bus by buffering both thedata (SDA) and the clock (SCL) lines, thus enabling virtuallyunlimited buses of 400 pF.
標(biāo)簽： Expandable 5channel 9518 PCA
上傳時(shí)間： 2013-10-23
上傳用戶：dumplin9
The PCA9519 is a 4-channel level translating I2C-bus/SMBus repeater that enables theprocessor low voltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O.while retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling the I2C-bus or SMBusmaximum capacitance of 400 pF on the higher voltage side. The SDA and SCL pins areover-voltage tolerant and are high-impedance when the PCA9519 is unpowered.
標(biāo)簽： 4channel transla level 9519
上傳時(shí)間： 2013-11-19
上傳用戶：jisiwole
The MAX3243E device consists of three line drivers, five line receivers, and a dual charge-pump circuit with±15-kV ESD (HBM and IEC61000-4-2, Air-Gap Discharge) and ±8-kV ESD (IEC61000-4-2, Contact Discharge)protection on serial-port connection pins. The device meets the requirements of TIA/EIA-232-F and provides theelectrical interface between an asynchronous communication controller and the serial-port connector. Thiscombination of drivers and receivers matches that needed for the typical serial port used in an IBM PC/AT, orcompatible. The charge pump and four small external capacitors allow operation from a single 3-V to 5.5-Vsupply. In addition, the device includes an always-active noninverting output (ROUT2B), which allowsapplications using the ring indicator to transmit data while the device is powered down. The device operates atdata signaling rates up to 250 kbit/s and a maximum of 30-V/ms driver output slew rate.
標(biāo)簽： MULTICHANNEL 5.5 TO RS
上傳時(shí)間： 2013-10-19
上傳用戶：ddddddd
The Philips family of Multiplexers and Switches consists of bi-directional translating switches controlled via the I2C or SMBus to fan out an upstream SCL/SDA pair to 2, 4 or 8 downstream channels of SCx/SDx pairs. The Multiplexers allow only one downstream channel to be selected at a time, while the Switches allow any individual downstream channel or combination of downstream channels to be selected, depending on the content of the programmable control register. Once one or several channels have been selected, the device acts as a wire, allowing the master on the upstream channel to send commands to devices on all the active downstream channels, and devices on the active downstream channels to communicate with each other and the master. External pull-up resistors are used to pull each individual channel up to the desired voltage level. Combined interrupt output and hardware reset input are device options that are featured.
上傳時(shí)間： 2013-10-11
上傳用戶：dianxin61
C51基本結(jié)構(gòu)程序設(shè)計(jì)1． 掌握if語(yǔ)句來(lái)實(shí)現(xiàn)選擇結(jié)構(gòu)，能利用if語(yǔ)句編寫相應(yīng)的分枝結(jié)構(gòu)的程序。在嵌套if語(yǔ)句中，一定要搞清楚else與哪個(gè)if結(jié)合的問(wèn)題。2．掌握switch語(yǔ)句來(lái)實(shí)現(xiàn)多向分枝選擇結(jié)構(gòu)，能利用switch語(yǔ)句編寫相應(yīng)的分枝結(jié)構(gòu)的程序。 3. 掌握循環(huán)語(yǔ)句的即初始化、循環(huán)體、循環(huán)控制及結(jié)束四個(gè)部分，并能進(jìn)行循環(huán)語(yǔ)句的程序設(shè)計(jì)。分別掌握f(shuō)or 語(yǔ)句、while語(yǔ)句以及do-while語(yǔ)句的使用語(yǔ)法及方法，能利用這三種循環(huán)結(jié)構(gòu)進(jìn)行循環(huán)程序設(shè)計(jì)，理解這三種語(yǔ)句的異同。4．理解并掌握continue、break語(yǔ)句在循環(huán)結(jié)構(gòu)和選擇結(jié)構(gòu)中的作用。對(duì)于goto語(yǔ)句，理解該語(yǔ)句優(yōu)缺點(diǎn)。C51語(yǔ)言是結(jié)構(gòu)化編程語(yǔ)言。結(jié)構(gòu)化語(yǔ)言的基本元素是模塊，它是程序的一部分．只有一個(gè)出口和一個(gè)入口．不允許有偶然的中途插入或以模塊的其它路徑退出。結(jié)構(gòu)化編程語(yǔ)言在沒(méi)有妥善保護(hù)或恢復(fù)堆棧和其它相關(guān)的寄存器之前，不應(yīng)隨便跳入或跳出一個(gè)模塊。因此使用這種結(jié)構(gòu)化語(yǔ)言進(jìn)行編程，當(dāng)要退出中斷時(shí)，堆棧不會(huì)因?yàn)槌绦蚴褂昧巳魏慰梢越邮艿拿疃罎ⅰ?nbsp; 結(jié)構(gòu)化程序由若干模塊組成，每個(gè)模塊中包含著若干個(gè)基本結(jié)構(gòu)，而每個(gè)基本結(jié)構(gòu)中可以有若干條語(yǔ)句。歸納起來(lái)，C51程序有順序結(jié)構(gòu)、選擇結(jié)構(gòu)、循環(huán)結(jié)構(gòu)共三種結(jié)構(gòu)。
標(biāo)簽： C51 基本結(jié)構(gòu) 程序設(shè)計(jì)
上傳時(shí)間： 2013-11-01
上傳用戶：四只眼
The μPSD32xx family, from ST, consists of Flash programmable system devices with a 8032 MicrocontrollerCore. Of these, the μPSD3234A and μPSD3254A are notable for having a complete implementationof the USB hardware directly on the chip, complying with the Universal Serial Bus Specification, Revision1.1.This application note describes a demonstration program that has been written for the DK3200 hardwaredemonstration kit (incorporating a μPSD3234A device). It gives the user an idea of how simple it is to workwith the device, using the HID class as a ready-made device driver for the USB connection.IN-APPLICATION-PROGRAMMING (IAP) AND IN-SYSTEM-PROGRAMMING (ISP)Since the μPSD contains two independent Flash memory arrays, the Micro Controller Unit (MCU) can executecode from one memory while erasing and programming the other. Product firmware updates in thefield can be reliably performed over any communication channel (such as CAN, Ethernet, UART, J1850)using this unique architecture. For In-Application-Programming (IAP), all code is updated through theMCU. The main advantage for the user is that the firmware can be updated remotely. The target applicationruns and takes care on its own program code and data memory.IAP is not the only method to program the firmware in μPSD devices. They can also be programmed usingIn-System-Programming (ISP). A IEEE1149.1-compliant JTAG interface is included on the μPSD. Withthis, the entire device can be rapidly programmed while soldered to the circuit board (Main Flash memory,Secondary Boot Flash memory, the PLD, and all configuration areas). This requires no MCU participation.The MCU is completely bypassed. So, the μPSD can be programmed or reprogrammed any time, anywhere, even when completely uncommitted.Both methods take place with the device in its normal hardware environment, soldered to a printed circuitboard. The IAP method cannot be used without previous use of ISP, because IAP utilizes a small amountof resident code to receive the service commands, and to perform the desired operations.
標(biāo)簽： Demonstration 3200 USB for
上傳時(shí)間： 2014-02-27
上傳用戶：zhangzhenyu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
標(biāo)簽： Signal Input Fall Rise
上傳時(shí)間： 2013-10-23
上傳用戶：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
標(biāo)簽： C16x 微控制器 輸入信號(hào) 時(shí)序圖
上傳時(shí)間： 2014-04-02
上傳用戶：han_zh
串行編程器源程序(Keil C語(yǔ)言)//FID=01:AT89C2051系列編程器//實(shí)現(xiàn)編程的讀，寫，擦等細(xì)節(jié)//AT89C2051的特殊處:給XTAL一個(gè)脈沖，地址計(jì)數(shù)加1;P1的引腳排列與AT89C51相反，需要用函數(shù)轉(zhuǎn)換#include <e51pro.h> #define C2051_P3_7 P1_0#define C2051_P1 P0//注意引腳排列相反#define C2051_P3_0 P1_1#define C2051_P3_1 P1_2#define C2051_XTAL P1_4#define C2051_P3_2 P1_5#define C2051_P3_3 P1_6#define C2051_P3_4 P1_7#define C2051_P3_5 P3_5 void InitPro01()//編程前的準(zhǔn)備工作{ SetVpp0V(); P0=0xff; P1=0xff; C2051_P3_5=1; C2051_XTAL=0; Delay_ms(20); nAddress=0x0000; SetVpp5V();} void ProOver01()//編程結(jié)束后的工作，設(shè)置合適的引腳電平{ SetVpp5V(); P0=0xff; P1=0xff; C2051_P3_5=1; C2051_XTAL=1;} BYTE GetData()//從P0口獲得數(shù)據(jù){ B_0=P0_7; B_1=P0_6; B_2=P0_5; B_3=P0_4; B_4=P0_3; B_5=P0_2; B_6=P0_1; B_7=P0_0; return B;} void SetData(BYTE DataByte)//轉(zhuǎn)換并設(shè)置P0口的數(shù)據(jù){ B=DataByte; P0_0=B_7; P0_1=B_6; P0_2=B_5; P0_3=B_4; P0_4=B_3; P0_5=B_2; P0_6=B_1; P0_7=B_0;} void ReadSign01()//讀特征字{ InitPro01(); Delay_ms(1);//----------------------------------------------------------------------------- //根據(jù)器件的DataSheet，設(shè)置相應(yīng)的編程控制信號(hào) C2051_P3_3=0; C2051_P3_4=0; C2051_P3_5=0; C2051_P3_7=0; Delay_ms(20); ComBuf[2]=GetData(); C2051_XTAL=1; C2051_XTAL=0; Delay_us(20); ComBuf[3]=GetData(); ComBuf[4]=0xff;//----------------------------------------------------------------------------- ProOver01();} void Erase01()//擦除器件{ InitPro01();//----------------------------------------------------------------------------- //根據(jù)器件的DataSheet，設(shè)置相應(yīng)的編程控制信號(hào) C2051_P3_3=1; C2051_P3_4=0; C2051_P3_5=0; C2051_P3_7=0; Delay_ms(1); SetVpp12V(); Delay_ms(1); C2051_P3_2=0; Delay_ms(10); C2051_P3_2=1; Delay_ms(1);//----------------------------------------------------------------------------- ProOver01();} BOOL Write01(BYTE Data)//寫器件{//----------------------------------------------------------------------------- //根據(jù)器件的DataSheet，設(shè)置相應(yīng)的編程控制信號(hào) //寫一個(gè)單元 C2051_P3_3=0; C2051_P3_4=1; C2051_P3_5=1; C2051_P3_7=1; SetData(Data); SetVpp12V(); Delay_us(20); C2051_P3_2=0; Delay_us(20); C2051_P3_2=1; Delay_us(20); SetVpp5V(); Delay_us(20); C2051_P3_4=0; Delay_ms(2); nTimeOut=0; P0=0xff; nTimeOut=0; while(!GetData()==Data)//效驗(yàn):循環(huán)讀，直到讀出與寫入的數(shù)相同 { nTimeOut++; if(nTimeOut>1000)//超時(shí)了 { return 0; } } C2051_XTAL=1; C2051_XTAL=0;//一個(gè)脈沖指向下一個(gè)單元//----------------------------------------------------------------------------- return 1;} BYTE Read01()//讀器件{ BYTE Data;//----------------------------------------------------------------------------- //根據(jù)器件的DataSheet，設(shè)置相應(yīng)的編程控制信號(hào) //讀一個(gè)單元 C2051_P3_3=0; C2051_P3_4=0; C2051_P3_5=1; C2051_P3_7=1; Data=GetData(); C2051_XTAL=1; C2051_XTAL=0;//一個(gè)脈沖指向下一個(gè)單元//----------------------------------------------------------------------------- return Data;} void Lock01()//寫鎖定位{ InitPro01();//先設(shè)置成編程狀態(tài)//----------------------------------------------------------------------------- //根據(jù)器件的DataSheet，設(shè)置相應(yīng)的編程控制信號(hào) if(ComBuf[2]>=1)//ComBuf[2]為鎖定位 { C2051_P3_3=1; C2051_P3_4=1; C2051_P3_5=1; C2051_P3_7=1; Delay_us(20); SetVpp12V(); Delay_us(20); C2051_P3_2=0; Delay_us(20); C2051_P3_2=1; Delay_us(20); SetVpp5V(); } if(ComBuf[2]>=2) { C2051_P3_3=1; C2051_P3_4=1; C2051_P3_5=0; C2051_P3_7=0; Delay_us(20); SetVpp12V(); Delay_us(20); C2051_P3_2=0; Delay_us(20); C2051_P3_2=1; Delay_us(20); SetVpp5V(); }//----------------------------------------------------------------------------- ProOver01();} void PreparePro01()//設(shè)置pw中的函數(shù)指針，讓主程序可以調(diào)用上面的函數(shù){ pw.fpInitPro=InitPro01; pw.fpReadSign=ReadSign01; pw.fpErase=Erase01; pw.fpWrite=Write01; pw.fpRead=Read01; pw.fpLock=Lock01; pw.fpProOver=ProOver01;}
上傳時(shí)間： 2013-11-12
上傳用戶：gut1234567
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