6小時(shí)學(xué)會(huì)labview, labview Six Hour Course – Instructor Notes This zip file contains material designed to give students a working knowledge of labview in a 6 hour timeframe. The contents are: Instructor Notes.doc – this document. labviewIntroduction-SixHour.ppt – a PowerPoint presentation containing screenshots and notes on the topics covered by the course. Convert C to F (Ex1).vi – Exercise 1 solution VI. Convert C to F (Ex2).vi – Exercise 2 solution subVI. Thermometer-DAQ (Ex2).vi – Exercise 2 solution VI. Temperature Monitor (Ex3).vi – Exercise 3 solution VI. Thermometer (Ex4).vi – Exercise 4 solution subVI. Convert C to F (Ex4).vi – Exercise 4 solution subVI. Temperature Logger (Ex4).vi – Exercise 4 solution VI. Multiplot Graph (Ex5).vi – Exercise 5 solution VI. Square Root (Ex6).vi – Exercise 6 solution VI. State Machine 1 (Ex7).vi – Exercise 7 solution VI. The slides can be presented in two three hour labs, or six one hour lectures. Depending on the time and resources available in class, you can choose whether to assign the exercises as homework or to be done in class. If you decide to assign the exercises in class, it is best to assign them in order with the presentation. This way the students can create VI’s while the relevant information is still fresh. The notes associated with the exercise slide should be sufficient to guide the students to a solution. The solution files included are one possible solution, but by no means the only solution.
標(biāo)簽： labview
上傳時(shí)間： 2013-10-13
上傳用戶：zjwangyichao
Abstract: while many questions still surround the creation and deployment of the smart grid, the need for a reliablecommunications infrastructure is indisputable. Developers of the IEEE 1901.2 standard identified difficult channel conditionscharacteristic of low-frequency powerline communications and implemented an orthogonal frequency division multiplexing (OFDM)architecture using advanced modulation and channel-coding techniques. This strategy helped to ensure a robust communicationsnetwork for the smart grid.
標(biāo)簽： 1901.2 OFDM IEEE 正交頻分復(fù)用
上傳時(shí)間： 2013-10-18
上傳用戶：myworkpost
Abstract: This application note illustrates the flexibility of the MAX7060 ASK/FSK transmitter. while the currently available evaluationkit (EV kit) has been optimized for the device's use in a specific frequency band (i.e., 288MHz to 390MHz), this document addresseshow the EV kit circuitry can be modified for improved operation at 433.92MHz, a frequency commonly used in Europe. Twoalternative match and filter configurations are presented: one for optimizing drain efficiency, the other for achieving higher transmitpower. Features and capabilities of earlier Maxim industrial, scientific, and medical radio-frequency (ISM-RF) transmitters areprovided, allowing comparison of the MAX7060 to its predecessors. Several design guidelines and cautions for using the MAX7060are discussed.
標(biāo)簽： ASK_FSK 7060 MAX ISM
上傳時(shí)間： 2013-11-14
上傳用戶：swaylong
Agilent AN 154 S-Parameter Design Application Note S參數(shù)的設(shè)計(jì)與應(yīng)用 The need for new high-frequency, solid-state circuitdesign techniques has been recognized both by microwaveengineers and circuit designers. These engineersare being asked to design solid state circuitsthat will operate at higher and higher frequencies.The development of microwave transistors andAgilent Technologies’ network analysis instrumentationsystems that permit complete network characterizationin the microwave frequency rangehave greatly assisted these engineers in their work.The Agilent Microwave Division’s lab staff hasdeveloped a high frequency circuit design seminarto assist their counterparts in R&D labs throughoutthe world. This seminar has been presentedin a number of locations in the United States andEurope.From the experience gained in presenting this originalseminar, we have developed a four-part videotape, S-Parameter Design Seminar. while the technologyof high frequency circuit design is everchanging, the concepts upon which this technologyhas been built are relatively invariant.The content of the S-Parameter Design Seminar isas follows:
標(biāo)簽： S參數(shù)
上傳時(shí)間： 2013-12-19
上傳用戶：aa54
This book evolved over the past ten years from a set of lecture notes developed while teaching the undergraduate Algorithms course at Berkeley and U.C. San Diego. Our way of teaching this course evolved tremendously over these years in a number of directions, partly to address our students' background (undeveloped formal skills outside of programming), and partly to reect the maturing of the eld in general, as we have come to see it. The notes increasingly crystallized into a narrative, and we progressively structured the course to emphasize the ?story line? implicit in the progression of the material. As a result, the topics were carefully selected and clustered. No attempt was made to be encyclopedic, and this freed us to include topics traditionally de-emphasized or omitted from most Algorithms books.
標(biāo)簽： Algorithms 算法
上傳時(shí)間： 2013-11-11
上傳用戶：JamesB
飛思卡爾智能車(chē)的舵機(jī)測(cè)試程序 #include <hidef.h> /* common defines and macros */#include <MC9S12XS128.h> /* derivative information */#pragma LINK_INFO DERIVATIVE "mc9s12xs128" void SetBusCLK_16M(void) { CLKSEL=0X00; PLLCTL_PLLON=1; //鎖相環(huán)電路允許位 SYNR=0x00 | 0x01; //SYNR=1 REFDV=0x80 | 0x01; POSTDIV=0x00; _asm(nop); _asm(nop); while(!(CRGFLG_LOCK==1)); CLKSEL_PLLSEL =1; } void PWM_01(void) { //舵機(jī)初始化 PWMCTL_CON01=1; //0和1聯(lián)合成16位PWM； PWMCAE_CAE1=0; //選擇輸出模式為左對(duì)齊輸出模式 PWMCNT01 = 0; //計(jì)數(shù)器清零； PWMPOL_PPOL1=1; //先輸出高電平，計(jì)數(shù)到DTY時(shí)，反轉(zhuǎn)電平 PWMPRCLK = 0X40; //clockA 不分頻,clockA=busclock=16MHz;CLK B 16分頻:1Mhz PWMSCLA = 0x08; //對(duì)clock SA 16分頻,pwm clock=clockA/16=1MHz; PWMCLK_PCLK1 = 1; //選擇clock SA做時(shí)鐘源 PWMPER01 = 20000; //周期20ms； 50Hz; PWMDTY01 = 1500; //高電平時(shí)間為1.5ms; PWME_PWME1 = 1;
標(biāo)簽： 飛思卡爾智能車(chē) 舵機(jī) 測(cè)試程序
上傳時(shí)間： 2013-11-04
上傳用戶：狗日的日子
目錄 C語(yǔ)言基礎(chǔ)知識(shí) C 語(yǔ)言簡(jiǎn)介 C 語(yǔ)言的特點(diǎn)… C 語(yǔ)言的發(fā)展和標(biāo)準(zhǔn)化…數(shù)據(jù)類(lèi)型、運(yùn)算、表達(dá)式和編譯預(yù)處理 數(shù)據(jù)類(lèi)型… 基本類(lèi)型與數(shù)據(jù)表示 整數(shù)類(lèi)型和整數(shù)的表示… 實(shí)數(shù)類(lèi)型和實(shí)數(shù)的表示… 字符類(lèi)型和字符的表示… 運(yùn)算符、表達(dá)式與計(jì)算… 算術(shù)運(yùn)算符 算術(shù)表達(dá)式 表達(dá)式的求值… 變量——概念、定義和使用… 變量的定義0 變量的使用：取值與賦值 預(yù)處理 文件包含命令… 宏定義與宏替換…邏輯判斷與運(yùn)算… 關(guān)系運(yùn)算和邏輯運(yùn)算 復(fù)雜條件的描述0 i f語(yǔ)句循環(huán)控制 whi le語(yǔ)句 for語(yǔ)句… 循環(huán)程序常用的若干機(jī)制 增量和減量運(yùn)算符（++、--） 逗號(hào)運(yùn)算符 控制結(jié)構(gòu)和控制語(yǔ)句 do-while循環(huán)結(jié)構(gòu)… 流程控制語(yǔ)句… goto語(yǔ)句… 開(kāi)關(guān)語(yǔ)句…函數(shù) 概述… 函數(shù)定義和程序的函數(shù)分解… 函數(shù)定義… 函數(shù)調(diào)用…數(shù)組 數(shù)組的概念、定義和使用 數(shù)組變量定義… 數(shù)組的使用 數(shù)組的初始化…結(jié)構(gòu) 結(jié)構(gòu)（struct） 結(jié)構(gòu)說(shuō)明與變量定義 結(jié)構(gòu)變量的初始化和使用 結(jié)構(gòu)與函數(shù) 處理結(jié)構(gòu)的函數(shù)0指針 指針的概念 指針操作… 指針作為函數(shù)的參數(shù) 與指針有關(guān)的一些問(wèn)題… 指針與數(shù)組 指向數(shù)組元素的指針 基于指針運(yùn)算的數(shù)組程序設(shè)計(jì) 數(shù)組參數(shù)與指針 字符指針與字符數(shù)組0
上傳時(shí)間： 2013-11-16
上傳用戶：asdkin
//------------------------------------------------------------------------------------//此程序?yàn)锳DC轉(zhuǎn)換程序，可以選擇向ADC0BUSY寫(xiě)1或用定時(shí)器0,1,2,3作為ADC的啟動(dòng)信號(hào)。////------------------------------------------------------------------------------------//頭文件定義//------------------------------------------------------------------------------------//#include <c8051f330.h> #include <stdio.h> //-----------------------------------------------------------------------------// 定義16位特殊功能寄存器//----------------------------------------------------------------------------- sfr16 ADC0 = 0xbd; sfr16 TMR0RL = 0xca; sfr16 TMR1RL = 0xca; sfr16 TMR2RL =0xca; sfr16 TMR3RL =0xca; sfr16 TMR0 = 0xCC; sfr16 TMR1 = 0xCC; sfr16 TMR2 = 0xcc; sfr16 TMR3 = 0xcc; //-----------------------------------------------------------------------------// 全局變量定義//-----------------------------------------------------------------------------char i;int result; //-----------------------------------------------------------------------------//定義常量//-----------------------------------------------------------------------------#define SYSCLK 49000000 #define SAMPLE_RATE 50000 //------------------------------------------------------------------------------------// 定義函數(shù)//------------------------------------------------------------------------------------void SYSCLK_Init (void);void PORT_Init (void);void Timer0_Init (int counts);void Timer1_Init (int counts);void Timer2_Init (int counts);void Timer3_Init (int counts);void ADC0_Init(void);void ADC0_ISR (void);void ADC0_CNVS_ADC0h(void);//------------------------------------------------------------------------------------// 主程序//------------------------------------------------------------------------------------ void main (void) { int ADCRESULT[50] ; int k; PCA0MD &= ~0x40; // 禁止看門(mén)狗 SYSCLK_Init (); PORT_Init (); Timer0_Init (SYSCLK/SAMPLE_RATE); //Timer1_Init (SYSCLK/SAMPLE_RATE); //選擇相應(yīng)的啟動(dòng)方式 //Timer2_Init (SYSCLK/SAMPLE_RATE); //Timer3_Init (SYSCLK/SAMPLE_RATE); ADC0_Init(); EA=1; while(1) { //ADC0_CNVS_ADC0h(); k=ADC0; ADCRESULT[i]=result; //此處設(shè)斷點(diǎn)，觀察ADCRESULT的結(jié)果 } }
上傳時(shí)間： 2013-10-13
上傳用戶：SimonQQ
溫濕度傳感器 sht11 仿真程序 sbit out =P3^0; //加熱口 //sbit input =P1^1;//檢測(cè)口 //sbit speek =P2^0;//報(bào)警 sbit clo =P3^7;//時(shí)鐘 sbit ST =P3^5;//開(kāi)始 sbit EOC =P3^6;//成功信號(hào) sbit gwei =P3^4;//個(gè)位 sbit swei =P3^3;//十位 sbit bwei =P3^2;//百位 sbit qwei =P3^1;//千位 sbit speak =P0^0;//報(bào)警音 sbit bjled =P0^1;//報(bào)警燈 sbit zcled =P0^2;//正常LED int count; uchar xianzhi;//取轉(zhuǎn)換結(jié)果 uchar seth;//高時(shí)間 uchar setl;//低時(shí)間 uchar seth_mi;//高時(shí)間 uchar setl_mi;//低時(shí)間 bit hlbz;//高低標(biāo)志 bit clbz; bit spbz; ///定時(shí)中斷程序/// void t0 (void) interrupt 1 using 0 { TH0=(65536-200)/256;//5ms*200=1000ms=1s TL0=(65536-200)%256; clo=!clo;//產(chǎn)生時(shí)鐘 if(count>5000) { if(hlbz) { if(seth_mi==0){seth_mi=seth;hlbz=0;out=0;} else seth_mi--; } if(!hlbz) { if(setl_mi==0){setl_mi=setl;hlbz=1;out=1;} else setl_mi--; } count=0; } else count++; } ///////////// ///////延時(shí)/////// delay(int i) { while(--i); } ///////顯示處理/////// xianshi() { int abcd=0; int i; for (i=0;i<5;i++) { abcd=xianzhi; gwei=1; swei=1; bwei=1; qwei=1; P1=dispcode[abcd/1000]; qwei=0; delay(70); qwei=1; abcd=abcd%1000; P1=dispcode[abcd/100]; bwei=0; delay(70); bwei=1; abcd=abcd%100; P1=dispcode[abcd/10]; swei=0; delay(70); swei=1; abcd=abcd%10; P1=dispcode[abcd]; gwei=0; delay(70); gwei=1; } } doing() { if(xianzhi>100) {bjled=0;speak=1;zcled=1;} else {bjled=1;speak=0;zcled=0;} } void main(void) { seth=60;//h60秒 setl=90;//l90秒 seth_mi=60;//h60秒 setl_mi=90;//l90秒 TMOD=0X01;//定時(shí)0 16位工作模式 TH0=(65536-200)/256; TL0=(65536-200)%256; TR0=1; //開(kāi)始計(jì)時(shí) ET0=1; //開(kāi)定時(shí)0中斷 EA=1; //開(kāi)全中斷 while(1) { ST=0; _nop_(); ST=1; _nop_(); ST=0; // EOC=0; xianshi(); while(!EOC) { xianshi(); } xianzhi=P2; xianshi(); doing(); } }
上傳時(shí)間： 2013-11-07
上傳用戶：我們的船長(zhǎng)
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-21
上傳用戶：wxqman
蟲(chóng)蟲(chóng)下載站版權(quán)所有 京ICP備2021023401號(hào)-1
