相 關(guān) 資 源

• Verilog module containing a synthesizable CRC function // * polynomial: (0 1 8) // * data width: 8免費(fèi)下載

  資源簡(jiǎn)介：Verilog module containing a synthesizable CRC function // * polynomial: (0 1 8) // * data width: 8

  標(biāo)簽： synthesizable containing polynomial function

  上傳時(shí)間： 2016-09-26

  上傳用戶(hù)：lacsx

• Verilog Overview n Basic Structure of a Verilog Model n Components of a Verilog Module – Ports –免費(fèi)下載

  資源簡(jiǎn)介：Verilog Overview n Basic Structure of a Verilog Model n Components of a Verilog Module – Ports – Data Types – Assigning Values and Numbers – Operators – Behavioral Modeling &#8226 Continuous Assignments &#8226 Procedural Block...

  標(biāo)簽： Verilog Components Structure Overview

  上傳時(shí)間： 2017-02-18

  上傳用戶(hù)：xinyuzhiqiwuwu

• crc_table.c is for reset seed( 0000 ) crc_table_1.c is for reset seed( ffff) CRC16_D8_m.v is a ver免費(fèi)下載

  資源簡(jiǎn)介：crc_table.c is for reset seed( 0000 ) crc_table_1.c is for reset seed( ffff) CRC16_D8_m.v is a verilog module of byte paralle crc. CRC16_D8_m_tb.v is the testbench file of above module.

  標(biāo)簽： crc_table reset seed for

  上傳時(shí)間： 2014-01-09

  上傳用戶(hù)：181992417

• Verilog HDL Synthesis, A Practical Primer免費(fèi)下載

  資源簡(jiǎn)介：·Verilog HDL Synthesis, A Practical Primer

  標(biāo)簽： nbsp Synthesis Practical Verilog

  上傳時(shí)間： 2013-04-24

  上傳用戶(hù)：muhongqing

• Use the verilog language write a MIPS CPU code, and have additional instruction, for example: select免費(fèi)下載

  資源簡(jiǎn)介：Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY,...

  標(biāo)簽： instruction additional language example

  上傳時(shí)間： 2014-01-17

  上傳用戶(hù)：yyyyyyyyyy

• This program demonstrates some function approximation capabilities of a Radial Basis function Networ免費(fèi)下載

  資源簡(jiǎn)介：This program demonstrates some function approximation capabilities of a Radial Basis function Network. The user supplies a set of training points which represent some "sample" points for some arbitrary curve. Next, the user specifies the n...

  標(biāo)簽： approximation demonstrates capabilities function

  上傳時(shí)間： 2014-01-01

  上傳用戶(hù)：zjf3110

• A fast customizable function for locating and measuring the peaks in noisy time-series signals.免費(fèi)下載

  資源簡(jiǎn)介：A fast customizable function for locating and measuring the peaks in noisy time-series signals.

  標(biāo)簽： customizable time-series measuring function

  上傳時(shí)間： 2013-12-19

  上傳用戶(hù)：changeboy

• A fast customizable function for locating and measuring the peaks in noisy time-series signals. Adju免費(fèi)下載

  資源簡(jiǎn)介：A fast customizable function for locating and measuring the peaks in noisy time-series signals. Adjustable parameters allow discrimination of "real" signal peaks from noise and background.

  標(biāo)簽： customizable time-series measuring function

  上傳時(shí)間： 2015-08-10

  上傳用戶(hù)：xhz1993

• A fast customizable function for locating and measuring the peaks in noisy time-series signals. Adju免費(fèi)下載

  資源簡(jiǎn)介：A fast customizable function for locating and measuring the peaks in noisy time-series signals. Adjustable parameters allow discrimination of "real" signal peaks from noise and background. Determines the position, height, and width of each ...

  標(biāo)簽： customizable time-series measuring function

  上傳時(shí)間： 2015-08-10

  上傳用戶(hù)：invtnewer

• Reducer: Given a dataset and a file containing a reduct, this program outputs a new dataset containi免費(fèi)下載

  資源簡(jiǎn)介：Reducer: Given a dataset and a file containing a reduct, this program outputs a new dataset containing only the attributes appearing in the reduct file.

  標(biāo)簽： dataset containing containi Reducer

  上傳時(shí)間： 2014-01-25

  上傳用戶(hù)：牛津鞋

• * This a software code module for a time-of-day clock object. * The clock may be fixed 12-hour, fi免費(fèi)下載

  資源簡(jiǎn)介：* This a software code module for a time-of-day clock object. * The clock may be fixed 12-hour, fixed 24-hour, or dynamically * configurable between these two types. Clock data can be accessed * as a binary number representing the num...

  標(biāo)簽： clock time-of-day software module

  上傳時(shí)間： 2013-12-07

  上傳用戶(hù)：llandlu

• Preparation of a function, even to the importation of n, the function call seeking +1/n 1/2+1/4+ ...免費(fèi)下載

  資源簡(jiǎn)介：Preparation of a function, even to the importation of n, the function call seeking +1/n 1/2+1/4+ .... When n is odd input, the function call 1/1+1/3+ ... +1/n (using function pointer)

  標(biāo)簽： function Preparation importation the

  上傳時(shí)間： 2014-01-21

  上傳用戶(hù)：semi1981

• The computer program for the maximum entropy estimation of a wave distribution function免費(fèi)下載

  資源簡(jiǎn)介：The computer program for the maximum entropy estimation of a wave distribution function

  標(biāo)簽： distribution estimation computer function

  上傳時(shí)間： 2015-11-03

  上傳用戶(hù)：lwwhust

• Verilog HDL Synthesis, A Practical Primer 學(xué)習(xí)Verilog HDL一本很不錯(cuò)的英文書(shū)免費(fèi)下載

  資源簡(jiǎn)介：Verilog HDL Synthesis, A Practical Primer 學(xué)習(xí)Verilog HDL一本很不錯(cuò)的英文書(shū)，比較透徹

  標(biāo)簽： Verilog HDL Synthesis Practical

  上傳時(shí)間： 2016-01-19

  上傳用戶(hù)：hongmo

• file upload have a good using function免費(fèi)下載

  資源簡(jiǎn)介：file upload have a good using function

  標(biāo)簽： function upload using file

  上傳時(shí)間： 2016-01-23

  上傳用戶(hù)：haoxiyizhong

• synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO免費(fèi)下載

  資源簡(jiǎn)介：synthesizable FIFO Model This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO...

  標(biāo)簽： FIFO implementation synthesizable synthesizable

  上傳時(shí)間： 2016-02-12

  上傳用戶(hù)：源弋弋

• The problem of ¯ nding a linear discriminant function will be formulated as a problem of minimi免費(fèi)下載

  資源簡(jiǎn)介：The problem of &macr nding a linear discriminant function will be formulated as a problem of minimizing a criterion function

  標(biāo)簽： problem discriminant formulated function

  上傳時(shí)間： 2014-11-30

  上傳用戶(hù)：15071087253

• All programs were tested using a breadboard containing a DS80C320, 32K Program memory, 32K Data me免費(fèi)下載

  資源簡(jiǎn)介：All programs were tested using a breadboard containing a DS80C320, 32K Program memory, 32K Data memory, two 8-segment bar graph LEDs/drivers, and an 11.0592 MHz crystal. The four 8-segment bar graph LEDs/drivers were connected to port...

  標(biāo)簽： breadboard containing 32K programs

  上傳時(shí)間： 2016-03-29

  上傳用戶(hù)：qq1604324866

• (2003 prentice-hall)verilog hdl：a guide to digital design and synthesis(2nd edition).rar免費(fèi)下載

  資源簡(jiǎn)介：(2003 prentice-hall)verilog hdl：a guide to digital design and synthesis(2nd edition).rar

  標(biāo)簽： prentice-hall synthesis digital edition

  上傳時(shí)間： 2014-01-17

  上傳用戶(hù)：teddysha

• Fax and soft modem source code. - Slow modem You can use this code to build a soft modem function免費(fèi)下載

  資源簡(jiǎn)介：Fax and soft modem source code. - Slow modem You can use this code to build a soft modem function in your embedded system. This is a slow version

  標(biāo)簽： modem soft code function

  上傳時(shí)間： 2016-08-04

  上傳用戶(hù)：wanghui2438

• Device pins that are not connected to a specific peripheral function are controlled by the GPIO reg免費(fèi)下載

  資源簡(jiǎn)介：Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simu ...

  標(biāo)簽： controlled peripheral are connected

  上傳時(shí)間： 2014-01-16

  上傳用戶(hù)：lijinchuan

• Snefru is a cryptographic hash function invented by Ralph Merkle which supports 128-bit and 256-bit免費(fèi)下載

  資源簡(jiǎn)介：Snefru is a cryptographic hash function invented by Ralph Merkle which supports 128-bit and 256-bit output.

  標(biāo)簽： cryptographic bit function invented

  上傳時(shí)間： 2014-01-13

  上傳用戶(hù)：wang0123456789

• 多項(xiàng)式擬合的MATLAB工具。只要具有以下幾個(gè)函數(shù) POLYFITN - A general n-dimensional polynomial fitting tool POLYVALN - An免費(fèi)下載

  資源簡(jiǎn)介：多項(xiàng)式擬合的MATLAB工具。只要具有以下幾個(gè)函數(shù) POLYFITN - A general n-dimensional polynomial fitting tool POLYVALN - An evaluation tool for polynomials produced by polyfitn POLYN2SYMPOLY - A conversion tool to generate a sympoly from the r...

  標(biāo)簽： n-dimensional polynomial POLYFITN POLYVALN

  上傳時(shí)間： 2014-11-30

  上傳用戶(hù)：s363994250

• 實(shí)用的I2C程序。This example describes a synthesizable implementation of a I2C.免費(fèi)下載

  資源簡(jiǎn)介：實(shí)用的I2C程序。This example describes a synthesizable implementation of a I2C.

  標(biāo)簽： implementation synthesizable describes example

  上傳時(shí)間： 2014-01-02

  上傳用戶(hù)：zhouli

• 與外部設(shè)備進(jìn)行成功連接的完整I2C程序。This example describes a synthesizable implementation of a I2C.免費(fèi)下載

  資源簡(jiǎn)介：與外部設(shè)備進(jìn)行成功連接的完整I2C程序。This example describes a synthesizable implementation of a I2C.

  標(biāo)簽： implementation synthesizable describes example

  上傳時(shí)間： 2017-01-24

  上傳用戶(hù)：jichenxi0730

• What is Verilog? ➥ Verilog HDL is a Hardware Description Language (HDL) ➥ Verilog HDL免費(fèi)下載

  資源簡(jiǎn)介：What is Verilog? &#10149 Verilog HDL is a Hardware Description Language (HDL) &#10149 Verilog HDL allows describe designs at a high level of abstraction as well as the lower implementation levels &#10149 Primary use of HDLs is the simul...

  標(biāo)簽： Verilog HDL 10149 Description

  上傳時(shí)間： 2017-02-18

  上傳用戶(hù)：

• verilog model of a PLL免費(fèi)下載

  資源簡(jiǎn)介：verilog model of a PLL

  標(biāo)簽： verilog model PLL of

  上傳時(shí)間： 2017-03-25

  上傳用戶(hù)：1159797854

• The Fat Fs module is a middleware that written in ANSI C. There is no platform dependence, so long a免費(fèi)下載

  資源簡(jiǎn)介：The Fat Fs module is a middleware that written in ANSI C. There is no platform dependence, so long as the compiler is in compliance with ANSI C. However it handles the system portable FAT structures. You must take the endian into considerat...

  標(biāo)簽： C. dependence middleware platform

  上傳時(shí)間： 2014-01-12

  上傳用戶(hù)：cccole0605

• 標(biāo)簽： Verilog 分頻器 N倍奇數(shù)分頻器.(Verilog) N_odd_divider.v / Verilog module N_odd_divider (免費(fèi)下載

  資源簡(jiǎn)介：標(biāo)簽： Verilog 分頻器 N倍奇數(shù)分頻器.(Verilog) N_odd_divider.v / Verilog module N_odd_divider (

  標(biāo)簽： Verilog N_odd_divider module 分頻器

  上傳時(shí)間： 2014-01-12

  上傳用戶(hù)：nanxia

• code for fpga is written in verilog,cardinality is a thing which is very important免費(fèi)下載

  資源簡(jiǎn)介：code for fpga is written in verilog,cardinality is a thing which is very important

  標(biāo)簽： cardinality important is written

  上傳時(shí)間： 2013-12-20

  上傳用戶(hù)：moerwang