The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct with minimal performance penalty. With their 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available fast GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications. Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.
上傳時間： 2014-12-30
上傳用戶：aysyzxzm
Abstract: With industrial/scientific/medical (ISM) band radio frequency (RF) products, often times users are new to the structure of Maxim's low pin-count transmitters andfully integrated superheterodyne receivers. This tutorial provides simple steps that can be taken to get the best performance out of these transmitters and receivers whileproviding techniques to measure the overall capability of the design.
上傳時間： 2013-11-02
上傳用戶：yph853211
重大消息:完美NRF24L01+的代替面世了,SI24R1,它與NORDIC 的 NRF24L01+是完全兼容的（SPI 的操作時序，寄存器定義，工作狀態 圖），可以相互通信，支持NRF24L01+的所有通信功能。Si24R 完全 PIN 對PIN 替換NORDIC 的NRF24L01+ ,只要在原來焊NRF24L01P 的 位置上焊上SI24R1，就可以正常通信，SI24R1 還可以與NRF24L01P 相互通信，最大功率做到7DB，靈敏度更高，功耗更低，價格更廉. 為廣大NORDIC 的用戶節約了不少的生產成本!
上傳時間： 2014-01-15
上傳用戶：ks201314
關于合成孔徑激光雷達中微弱光電信號的檢測技術,分析了PIN光電二極管的主要噪聲來源,設計了偏置電路和濾波電路;鑒于高頻效應的影響,合理使用電磁屏蔽等措施。
上傳時間： 2014-12-30
上傳用戶：thinode
The LTC®3207/LTC3207-1 is a 600mA LED/Camera driverwhich illuminates 12 Universal LEDs (ULEDs) and onecamera fl ash LED. The ULEDs are considered universalbecause they may be individually turned on or off, setin general purpose output (GPO) mode, set to blink at aselected on-time and period, or gradate on and off at aselected gradation rate. This device also has an externalenable (ENU) pin that may be used to blink, gradate, orturn on/off the LEDs without using the I2C bus. This may beuseful if the microprocessor is in sleep or standby mode. Ifused properly, these features may save valuable memoryspace, programming time, and reduce the I2C traffi c.
上傳時間： 2014-01-04
上傳用戶：LANCE
Cadence 應用注意事項 1、 PCB 工藝規則 以下規則可能隨中國國內加工工藝提高而變化 1.1. 不同元件間的焊盤間隙：大于等于 40mil(1mm)，以保證各種批量在線焊板的需要。 1.2. 焊盤尺寸：粘錫部分的寬度保證大于等于 10mil(0.254mm)，如果焊腳(pin)較高，應 修剪；如果不能修剪的，相應焊盤應增大….. 1.3. 機械過孔最小孔徑：大于等于 6mil(0.15mm)。小于此尺寸將使用激光打孔，為國內 **************************************************************************************** 各種化工 石油 電子 制造 機械 編程 紡織等等各類電腦軟件, 歡迎咨詢 ------------------------------------------------------------------------------------ 聯系QQ：1270846518 Email: gjtsoft@qq.com 即時咨詢或留言：http://gjtsoft.53kf.com 電話: 18605590805 短信發送軟件名稱, 我們會第一時間為您回復 **************************************************************************************** 大多數 PCB廠家所不能接受。
上傳時間： 2013-10-19
上傳用戶：黃蛋的蛋黃
完整性高的FPGA-PCB系統化協同設計工具 Cadence OrCAD and Allegro FPGA System Planner便可滿足較復雜的設計及在設計初級產生最佳的I/O引腳規劃，并可透過FSP做系統化的設計規劃，同時整合logic、schematic、PCB同步規劃單個或多個FPGA pin的最佳化及layout placement，借由整合式的界面以減少重復在design及PCB Layout的測試及修正的過程及溝通時間，甚至透過最佳化的pin mapping、placement后可節省更多的走線空間或疊構。 Specifying Design Intent 在FSP整合工具內可直接由零件庫選取要擺放的零件，而這些零件可直接使用PCB內的包裝，預先讓我們同步規劃FPGA設計及在PCB的placement。
標簽： Allegro Planner System FPGA
上傳時間： 2013-11-06
上傳用戶：wwwe
本軟件是關于MAX338, MAX339的英文數據手冊：MAX338, MAX339 8通道/雙4通道、低泄漏、CMOS模擬多路復用器 The MAX338/MAX339 are monolithic, CMOS analog multiplexers (muxes). The 8-channel MAX338 is designed to connect one of eight inputs to a common output by control of a 3-bit binary address. The dual, 4-channel MAX339 is designed to connect one of four inputs to a common output by control of a 2-bit binary address. Both devices can be used as either a mux or a demux. On-resistance is 400Ω max, and the devices conduct current equally well in both directions. These muxes feature extremely low off leakages (less than 20pA at +25°C), and extremely low on-channel leakages (less than 50pA at +25°C). The new design offers guaranteed low charge injection (1.5pC typ) and electrostatic discharge (ESD) protection greater than 2000V, per method 3015.7. These improved muxes are pin-compatible upgrades for the industry-standard DG508A and DG509A. For similar Maxim devices with lower leakage and charge injection but higher on-resistance, see the MAX328 and MAX329.
上傳時間： 2013-11-12
上傳用戶：18711024007
This example provides a description of how to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sends the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must end by '\r'character (keypad ENTER button). Each byte received is retransmitted to theHyperterminal. The string that you have entered is stored in the RxBuffer array. The receivebuffer have a RxBufferSize bytes as maximum. The USART2 is configured as follow: - BaudRate = 115200 baud - Word Length = 8 Bits - One Stop Bit - No parity - Hardware flow control enabled (RTS and CTS signals) - Receive and transmit enabled - USART Clock disabled - USART CPOL: Clock is active low - USART CPHA: Data is captured on the second edge - USART LastBit: The clock pulse of the last data bit is not output to the SCLK pin
上傳時間： 2013-10-31
上傳用戶：yy_cn
This example shows how to update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI). The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is generated and in the WWDGISR the counter is refreshed to prevent a WWDG reset and led connected to PC.07is toggled.The EXTI line9 is connected to PB.09 pin and configured to generate an interrupton falling edge.In the NVIC, EXTI line9 to 5 interrupt vector is enabled with priority equal to 0and the WWDG interrupt vector is enabled with priority equal to 1 (EXTI IT > WWDG IT). The EXTI Line9 will be used to simulate a software failure: once the EXTI line9event occurs (by pressing Key push-button on EVAL board) the correspondent interruptis served, in the ISR the led connected to PC.07 is turned off and the EXTI line9pending bit is not cleared. So the CPU will execute indefinitely EXTI line9 ISR andthe WWDG ISR will never be entered(WWDG counter not updated). As result, when theWWDG counter falls to 3Fh the WWDG reset occurs.If the EXTI line9 event don抰 occurs the WWDG counter is indefinitely refreshed inthe WWDG ISR which prevent from WWDG reset. If the WWDG reset is generated, after resuming from reset a led connected to PC.06is turned on. In this example the system is clocked by the HSE(8MHz).
上傳時間： 2013-11-11
上傳用戶：gundamwzc
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