作為一種獨立于處理器的局部總線,PCI非常適用于網(wǎng)絡(luò)適配器、硬盤驅(qū)動器、全動態(tài)視頻卡、圖形卡及各類高速外設(shè)。據(jù)稱,目前有90%的Pentium處理器采用PCI做為系統(tǒng)總線。
上傳時間： 2013-11-07
上傳用戶：liaocs77
PCI Express是由Intel，Dell，Compaq，IBM，Microsoft等PCI SIG聯(lián)合成立的Arapahoe Work Group共同草擬并推舉成取代PCI總線標準的下一代標準。PCI Express利用串行的連接特點能輕松將數(shù)據(jù)傳輸速度提到一個很高的頻率，達到遠遠超出PCI總線的傳輸速率。一個PCI Express連接可以被配置成x1，x2，x4，x8，x12，x16和x32的數(shù)據(jù)帶寬。x1的通道能實現(xiàn)單向312.5 MB／s（2.5 Gb／s）的傳輸速率。Xilinx公司的Virtex5系列FPGA芯片內(nèi)嵌PCI-ExpressEndpoint Block硬核，為實現(xiàn)單片可配置PCI-Express總線解決方案提供了可能。 本文在研究PCI-Express接口協(xié)議和PCI-Express Endpoint Block硬核的基礎(chǔ)上，使用Virtex5LXT50 FPGA芯片設(shè)計PCI Express接口硬件電路，實現(xiàn)PCI-Express數(shù)據(jù)傳輸
上傳時間： 2013-12-27
上傳用戶：wtrl
The Virtex-4 features, such as the programmable IDELAY and built-in FIFO support, simplifythe bridging of a high-speed, PCI-X core to large amounts of DDR-SDRAM memory. Onechallenge is meeting the PCI-X target initial latency specification. PCI-X Protocol Addendum tothe PCI Local Bus Specification Revision 2.0a ([Ref 6]) dictates that when a target signals adata transfer, "the target must do so within 16 clocks of the assertion of FRAME#." PCItermination transactions, such as Split Response/Complete, are commonly used to meet thelatency specifications. This method adds complexity to the design, as well as additional systemlatency. Another solution is to increase the ratio of the memory frequency to the PCI-X busfrequency. However, this solution increases the required power and clock resource usage.
上傳時間： 2013-11-24
上傳用戶：18707733937
PCI-PCI 橋啟動時，一般需要從EEPROM 預(yù)讀取配置數(shù)據(jù)。更改EEPROM中的數(shù)據(jù)一般需要專用的燒結(jié)器，這給調(diào)試過程帶來不便。尤其是采用表貼封裝的EEPROM。本文以Intel 公司的Dec21554PCI-PCI 橋為例，介紹一種在線讀寫EEPROM 的方法。EEPROM選用的是ATMEL 公司生產(chǎn)的AT93LC66，4Kbit，按512×8bit 組織。
上傳時間： 2013-11-08
上傳用戶：trepb001
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標簽： pci PCB 設(shè)計規(guī)范
上傳時間： 2014-01-24
上傳用戶：s363994250
利用研華數(shù)據(jù)采集卡實現(xiàn)數(shù)據(jù)采集的方法介紹
標簽： 數(shù)據(jù)采集 系統(tǒng)應(yīng)用 研華 編程
上傳時間： 2013-10-19
上傳用戶：onewq
PCI-E是一種高速傳輸總線形式。
標簽： PCI-E 8622 數(shù)據(jù)采集卡
上傳時間： 2013-12-18
上傳用戶：宋桃子
PCI-1734快速安裝使用手冊PCI-1734快速安裝使用手冊PCI-1734快速安裝使用手冊PCI-1734快速安裝使用手冊PCI-1734快速安裝使用手冊PCI-1734快速安裝使用手冊PCI-1734快速安裝使用手冊
上傳時間： 2013-10-22
上傳用戶：ssz1990
本文介紹一種基于PCI Express 總線的高速數(shù)據(jù)采集卡的設(shè)計方案及功能實現(xiàn)。給出系統(tǒng)的基本結(jié)構(gòu)及單元組成，重點闡述系統(tǒng)硬件設(shè)計的關(guān)鍵技術(shù)和本地總線的控制邏輯，詳細探討了基于DriverWorks 的設(shè)備驅(qū)動程序的開發(fā)以及上層應(yīng)用軟件的設(shè)計。該系統(tǒng)通過實踐驗證，可用于衛(wèi)星下行高速數(shù)據(jù)的接收并可適用于其他高速數(shù)據(jù)采集與處理系統(tǒng)。關(guān)鍵詞：PCI Express 總線 PCIE PEX8311 DMA 板卡驅(qū)動 隨著空間科學(xué)和空間電子學(xué)技術(shù)的飛速發(fā)展，空間科學(xué)實驗的種類和數(shù)量以及科學(xué)實驗所產(chǎn)生的數(shù)據(jù)量不斷增加。為了使地面接收處理系統(tǒng)能夠?qū)崟r處理和顯示科學(xué)圖像數(shù)據(jù)，必須要設(shè)計出新的地面數(shù)據(jù)接收處理系統(tǒng)，實現(xiàn)大量高速數(shù)據(jù)的正確接收采集、處理以及存儲。為了滿足地面系統(tǒng)的要求，并為以后的計算機系統(tǒng)升級提供更廣闊的空間，本系統(tǒng)擬采用第三代I/O 互連技術(shù)PCI Express（簡稱PCI-E）作為本數(shù)據(jù)采集卡的進機總線形式。本文通過對PCI-E 總線專用接口芯片PLX 公司的PEX8311 性能分析，特別是對突發(fā)讀、寫和DMA讀操作的時序研究，設(shè)計出本地總線的可編程控制邏輯，并詳細討論了整個PCI-E 高速數(shù)據(jù)采集卡的硬件設(shè)計方案，以及WDM 驅(qū)動程序和上層應(yīng)用程序的設(shè)計方法。
上傳時間： 2013-10-28
上傳用戶：tianyi996
瀏覽所有的PCI設(shè)備
上傳時間： 2015-01-03
上傳用戶：zsjinju
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