With the Altera Nios II embedded processor, you as the system designercan accelerate time-critical software ALGORITHMS by adding custominstructions to the Nios II processor instruction set. Using custominstructions, you can reduce a complex sequence of standard instructionsto a single instruction implemented in hardware. You can use this featurefor a variety of applications, for example, to optimize software innerloops for digital signal processing (DSP), packet header processing, andcomputation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphicaluser interface (GUI) used to add up to 256 custom instructions to theNios II processor
上傳時間： 2013-11-07
上傳用戶：swing
Nios II定制指令用戶指南：With the Altera Nios II embedded processor, you as the system designer can accelerate time-critical software ALGORITHMS by adding custom instructions to the Nios II processor instruction set. Using custom instructions, you can reduce a complex sequence of standard instructions to a single instruction implemented in hardware. You can use this feature for a variety of applications, for example, to optimize software inner loops for digital signal processing (DSP), packet header processing, and computation-intensive applications. The Nios II configuration wizard,part of the Quartus® II software’s SOPC Builder, provides a graphical user interface (GUI) used to add up to 256 custom instructions to the Nios II processor. The custom instruction logic connects directly to the Nios II arithmetic logic unit (ALU) as shown in Figure 1–1.
上傳時間： 2013-10-12
上傳用戶：kang1923
WP409利用Xilinx FPGA打造出高端比特精度和周期精度浮點DSP算法實現方案： High-Level Implementation of Bit- and Cycle-Accurate Floating-Point DSP ALGORITHMS with Xilinx FPGAs
上傳時間： 2013-10-21
上傳用戶：huql11633
The power of programmability gives industrial automation designers a highly efficient， cost-effective alternative to traditional motor control units （MCUs）。 The parallel-processing power， fast computational speeds， and connectivity versatility of Xilinx® FPGAs can accelerate the implementation of advanced motor control ALGORITHMS such as Field Oriented Control （FOC）。 Additionally， Xilinx devices lower costs with greater on-chip integration of system components and shorten latencies with high-performance digital signal processing （DSP） that can tackle compute-intensive functions such as PID Controller， Clark/Park transforms， and Space Vector PWM. The Xilinx Spartan®-6 FPGA Motor Control Development Kit gives designers an ideal starting point for evaluating time-saving， proven， motor-control reference designs. The kit also shortens the process of developing custom control capabilities， with integrated peripheral functions （Ethernet， PowerLink， and PCI® Express）， a motor-control FPGA mezzanine card （FMC） with built-in Texas Instruments motor drivers and high-precision Delta-Sigma modulators， and prototyping support for evaluating alternative front-end circuitry.
上傳時間： 2013-10-28
上傳用戶：wujijunshi
CGAL is a collaborative effort of several sites in Europe and Israel. The goal is to make the most important of the solutions and methods developed in computational geometry available to users in industry and academia in a C++ library. The goal is to provide easy access to useful, reliable geometric ALGORITHMS
標簽： collaborative several Europe Israel
上傳時間： 2015-01-09
上傳用戶：refent
使用VB寫的加密算法庫，包括Blowfish, IDEA, Triple DES (3DES), DES, DESE, Gost, Skipjack, TEA, Cast5, Serpent-128, Serpent-192, Serpent-256, Rijndael-128, Rijndael-192, Rijndael-256, RC2, RC4, and Twofish), six popular hash ALGORITHMS (SHA-1, SHA-256, MD2, MD4, MD5, and RipeMD), 還有 Huffman和Base64算法.
上傳時間： 2014-12-21
上傳用戶：zhichenglu
推薦一個快速壓縮算法，本人試過，很好用，詳細說明請參看：http://www.codeguru.com/Cpp/Cpp/ALGORITHMS/compression/article.php/c7043/
標簽： 壓縮算法
上傳時間： 2014-01-10
上傳用戶：yyq123456789
算法ebook(10部算法經典著作的合集) 算法ebook> 10部算法經典著作的合集 chm格式 (1)Fundamentals of Data Structures by Ellis Horowitz and Sartaj Sahni (2)Data Structures, ALGORITHMS and Program Style Using C by James F. Korsh and Leonard J. Garrett (3)Data Structures and Algorithm Analysis in C by Mark Allen Weiss (4)Data Structures: From Arrays to Priority Queues by Wayne Amsbury (5)Information Retrieval: Data Structures & ALGORITHMS edited by William B. Frakes and Ricardo Baeza-Yates (6)Introduction to ALGORITHMS by Thomas H. Cormen, Charles E. Leiserson, and Ronald L. Rivest (7)Practical Data Structures in C++ by Bryan Flamig (8)Reliable Data Structures in C by Thomas Plum (9)Data Structures and ALGORITHMS Alfred V. Aho, Bell Laboratories, Murray Hill, New Jersey John E. Hopcroft, Cornell University, Ithaca, New York Jeffrey D. Ullman, Stanford University, Stanford, California (10)DDJ ALGORITHMS and Data Structures Articles
標簽： ebook Fundamentals Structures Ellis
上傳時間： 2015-04-04
上傳用戶：tfyt
FlexCompress is a high-speed compression library developed to provide archive functionality for your applications. This solution provides flexible compression and strong encryption ALGORITHMS that allows you to integrate archiving or backup features into your programs in a fast and easy way.
標簽： functionality FlexCompress compression high-speed
上傳時間： 2015-04-04
上傳用戶：s363994250
自適應(Adaptive)神經網絡源程序 The adaptive Neural Network Library is a collection of blocks that implement several Adaptive Neural Networks featuring different adaptation ALGORITHMS.~..~ There are 11 blocks that implement basically these 5 kinds of neural networks: 1) Adaptive Linear Network (ADALINE) 2) Multilayer Layer Perceptron with Extended Backpropagation algorithm (EBPA) 3) Radial Basis Functions (RBF) Networks 4) RBF Networks with Extended Minimal Resource Allocating algorithm (EMRAN) 5) RBF and Piecewise Linear Networks with Dynamic Cell Structure (DCS) algorithm A simulink example regarding the approximation of a scalar nonlinear function of 4 variables
標簽： collection implement Adaptive adaptive
上傳時間： 2015-04-09
上傳用戶：ywqaxiwang
