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ALWAYS

RISK+COMMUNICATION

The fi rst edition of this book came about because Regina Lundgren had ALWAYS been fascinated with communication. She started writing novels in the third grade. When she was asked on her fi rst day at the University of Washington what she hoped to do with her degree in scientifi c and technical communication, she replied, “I want to write environ- mental impact statements.” When Patricia Clark hired her to work at the Pacifi c Northwest National Laboratory to do just that, she was overjoyed.

標簽： COMMUNICATION RISK

上傳時間： 2020-06-01

上傳用戶：shancjb
SDN Software Defined Networks

The first question most readers of an O’Reilly book might ask is about the choice of the cover animal. In this case, “why a duck?” Well, for the record, our first choice was a unicorn decked out in glitter and a rainbow sash. That response ALWAYS gets a laugh (we are sure you just giggled a little), but it also brings to the surface a common perception of software-defined networks among many expe‐ rienced network professionals. Although we think there is some truth to this perception, there is certainly more meat than myth to this unicorn.

標簽： Networks Software Defined SDN

上傳時間： 2020-06-01

上傳用戶：shancjb
開關電源設計（英文版）

It all started rather innocuously. I walked into Dr GT Murthy’s office one fine day, andchanged my life. “Doc” was then the General Manager, Central R&D, of a very largeelectrical company headquartered in Bombay. In his new state-of-the-art electronics center,he had hand-picked some of India’s best engineers (over a hundred already) ever assembledunder one roof. Luckily, he too was originally a Physicist, and that certainly helped me gainsome empathy. Nowadays he is in retirement, but I will ALWAYS remember him as athoroughly fair, honest and facts-oriented person, who led by example. There were severalthings I absorbed from him that are very much part of my basic engineering persona today.You can certainly look upon this book as an extension of what Doc started many years agoin India … because that’s what it really is! I certainly wouldn’t be here today if I hadn’t metDoc. And in fact, several of the brash, high-flying managers I’ve met in recent years,desperately need some sort of crash course in technology and human values from Doc!

標簽： 開關電源

上傳時間： 2021-11-23

上傳用戶：
FPGA片內FIFO讀寫測試Verilog邏輯源碼Quartus工程文件+文檔說明使用 FPGA

FPGA片內FIFO讀寫測試Verilog邏輯源碼Quartus工程文件+文檔說明，使用 FPGA 內部的 FIFO 以及程序對該 FIFO 的數據讀寫操作。FPGA型號Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////module fifo_test( input clk, //50MHz時鐘 input rst_n //復位信號，低電平有效 );//-----------------------------------------------------------localparam W_IDLE = 1;localparam W_FIFO = 2; localparam R_IDLE = 1;localparam R_FIFO = 2; reg[2:0] write_state;reg[2:0] next_write_state;reg[2:0] read_state;reg[2:0] next_read_state;reg[15:0] w_data; //FIFO寫數據wire wr_en; //FIFO寫使能wire rd_en; //FIFO讀使能wire[15:0] r_data; //FIFO讀數據wire full; //FIFO滿信號 wire empty; //FIFO空信號 wire[8:0] rd_data_count; wire[8:0] wr_data_count; ///產生FIFO寫入的數據ALWAYS@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) write_state <= W_IDLE; else write_state <= next_write_state;endALWAYS@(*)begin case(write_state) W_IDLE: if(empty == 1'b1) //FIFO空，開始寫FIFO next_write_state <= W_FIFO; else next_write_state <= W_IDLE; W_FIFO: if(full == 1'b1) //FIFO滿 next_write_state <= W_IDLE; else next_write_state <= W_FIFO; default: next_write_state <= W_IDLE; endcaseendassign wr_en = (next_write_state == W_FIFO) ? 1'b1 : 1'b0; ALWAYS@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) w_data <= 16'd0; else if (wr_en == 1'b1) w_data <= w_data + 1'b1; else w_data <= 16'd0; end///產生FIFO讀的數據ALWAYS@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) read_state <= R_IDLE; else read_state <= next_read_state;endALWAYS@(*)begin case(read_state) R_IDLE: if(full == 1'b1) //FIFO滿, 開始讀FIFO next_read_state <= R_FIFO; else next_read_state <= R_IDLE; R_FIFO: if(empty == 1'b1)

標簽： fpga fifo verilog quartus

上傳時間： 2021-12-19

上傳用戶：20125101110
基于Multisim和LabVIEW的虛實結合數字電路實驗教學

實驗教學一直是工科教學中不可或缺的組成部分,對培養學生的動手能力,獨立思考能力,創新思維與發散思維具有重要的作用。針對目前電路教學實驗中電路仿真實驗與實物電路實驗各自獨立,無法統一問題,提出將仿真電路實驗與實物電路實驗有機的結合同步操作,并使用Web發布實現遠程實驗操作。采用Multisim作為電路實驗仿真平臺,NI Eiviss II作為實物電路實驗硬件平臺,運用LabVIEW整合Multisim電路仿真實驗與實物電路實驗,實現仿真與實物實驗有機結合,兩種實驗可同步進行。學生在仿真實驗中先可探索實驗,然后做實物實驗。同時運用LabVIEW開發出實驗過程人機交互操作接口界面,使用過程中效果良好。Experimental teaching has ALWAYS been an indispensable part of engineering education.And it ALWAYS plays an important role in cultivating students'practical ability,independent thinking ability,innovative thinking and divergent thinking.But simulation experiment and physical experiment cannot be unified in the circuit teaching experiment at present.In order to solve this problem,this paper proposes to combine organically the simulation circuit experiment with physical circuit experiment,and synchronously operate them.This paper uses the WEB publishing to achieve remote experimental operation.Multisim is used as the circuit simulation platform,and NI Eiviss II is used as the physical circuit hardware platform.Multisim circuit simulation experiment and physical circuit experiment are implemented by LabVIEW to realize the combination of simulation experiment and physical experiment.Students do explore experiments in simulation experiment firstly,and then do physical experiment.And this paper uses LabVIEW to develop the experimental man-machine interface.

標簽： multisim labview

上傳時間： 2022-04-05

上傳用戶：
Verilog的135個經典設計實例

【例3.1]4位全加器module adder 4（cout，sum i na，i nb，cin）；output[3：0]sum output cout；input[3：0]i na，i nb；input cin；assign（cout，suml=i na +i nb+ci n；endmodule【例3.2]4位計數器module count 4（out，reset，clk）；output[3：0]out；input reset，cl k；regl 3：01 out；ALWAYS@posedge clk）

標簽： verilog

上傳時間： 2022-06-16

上傳用戶：canderile