-
Virtual plants integrating Architectural and physiological models
標(biāo)簽：
Architectural
physiological
integrating
Virtual
上傳時(shí)間：
2016-03-28
上傳用戶(hù)：蟲(chóng)蟲(chóng)蟲(chóng)蟲(chóng)蟲(chóng)蟲(chóng)
-
I/O Kit Fundamentals
Chapter 1 What Is the I/O Kit?
Chapter 2 Architectural Overview
Chapter 3 The I/O Registry
Chapter 4 Driver and Device Matching
Chapter 5 The Base Classes
Chapter 6 I/O Kit Families
Chapter 7 Handling Events
Chapter 8 Managing Data
Chapter 9 Managing Power and Device Removal
Appendix A I/O Kit Family Reference
Chapter 10 Base and Helper Class Hierarchy
標(biāo)簽：
Chapter
Architectural
Fundamentals
Kit
上傳時(shí)間：
2014-01-04
上傳用戶(hù)：蟲(chóng)蟲(chóng)蟲(chóng)蟲(chóng)蟲(chóng)蟲(chóng)
-
MCSÉ-51 Programmer's Guide and Instruction Set
The information presented in this chapter is collected from the MCSÉ-51 Architectural Overview and the HardwareDescription of the 8051, 8052 and 80C51 chapters of this book. The material has been selected and rearranged toform a quick and convenient reference for the programmers of the MCS-51. This guide pertains specifically to the8051, 8052 and 80C51.
標(biāo)簽：
Program
Eacute
MCS
51
上傳時(shí)間：
2013-11-13
上傳用戶(hù)：hj_18
-
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC Architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly enhanced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽：
UltraScale
Xilinx
架構(gòu)
上傳時(shí)間：
2013-11-13
上傳用戶(hù)：瓦力瓦力hong
-
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC Architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly enhanced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽：
UltraScale
Xilinx
架構(gòu)
上傳時(shí)間：
2013-11-21
上傳用戶(hù)：wxqman
-
The TMS320LF240xA and TMS320LC240xA devices, new members of the TMS320C24x generation of
digital signal processor (DSP) controllers, are part of the TMS320C2000 platform of fixed-point DSPs. The
240xA devices offer the enhanced TMS320 DSP Architectural design of the C2xx core CPU for low-cost,
low-power, and high-performance processing capabilities. Several advanced peripherals, optimized for digital
motor and motion control applications, have been integrated to provide a true single-chip DSP controller. While
code-compatible with the existing C24x DSP controller devices, the 240xA offers increased processing
performance (40 MIPS) and a higher level of peripheral integration. See the TMS320x240xA Device Summary
section for device-specific features.
標(biāo)簽：
TMS
320
generation
240
上傳時(shí)間：
2013-12-16
上傳用戶(hù)：GavinNeko
-
Java Media APIs: Cross-Platform Imaging, Media, and Visualization presents integrated Java media solutions that demonstrate the best practices for using this diverse collection. According to Sun MicroSystems, "This set of APIs supports the integration of audio and video clips, animated presentations, 2D fonts, graphics, and images, as well as speech input/output and 3D models." By presenting each API in the context of its appropriate use within an integrated media application, the authors both illustrate the potential of the APIs and offer the Architectural guidance necessary to build compelling programs.
標(biāo)簽：
Media
Java
Cross-Platform
Visualization
上傳時(shí)間：
2013-12-04
上傳用戶(hù)：hanli8870
-
With this example-driven book, you get a quick, practical, and thorough introduction to Java s API for XML Web Services (JAX-WS) and the Java API for RESTful Web Services (JAX-RS). Java Web Services: Up and Running takes a clear, no-nonsense approach to these technologies by providing you with a mix of Architectural overview, complete working code examples, and short yet precise instructions for compiling, deploying, and executing a sample application. You ll not only learn how to write web services from scratch, but also how to integrate existing services into your Java applications. All the source code for the examples is available from the book s companion website.
標(biāo)簽：
example-driven
introduction
practical
thorough
上傳時(shí)間：
2013-12-18
上傳用戶(hù)：lnnn30
-
A programmable digital signal processor (PDSP) is a special-purpose microprocessor
with specialized architecture and instruction set for implementing DSP
algorithms. Typical Architectural features include multiple memory partitions (onchip,
off-chip, data memory, program memory, etc.), multiple (generally pipelined)
arithmetic and logic units (ALUs), nonuniform register sets, and extensive
hardware numeric support [1,2]. Single-chip PDSPs have become increasingly
popular for real-time DSP applications [3,4].
標(biāo)簽：
special-purpose
microprocessor
programmable
specialized
上傳時(shí)間：
2017-08-13
上傳用戶(hù)：腳趾頭
-
Never have telecommunications operations and network management been so
important. Never has it been more important to move away from practices that date
back to the very beginning of the telecommunications industry. Building and con-
necting systems internally at low cost, on an as - needed basis, and adding software
for supporting new networks and services without an overall Architectural design
will not be cost effective for the future. Defi ning operations and network manage-
ment requirements at the 11th hour for new technologies, networks, and services
deployments must also change.
標(biāo)簽：
Telecommunications
Generation
Networks
Next
上傳時(shí)間：
2020-05-31
上傳用戶(hù)：shancjb
