In the past decade, the size and complexity of manyFPGA designs exceeds the time and resourcesavailable to most design teams, making the use andreuse of Intellectual Property (IP) imperative.However, integrating numerous IP blocks acquiredfrom both internal and external sources can be adaunting challenge that often extends, rather thanshortens, design time. As today's designs integrateincreasing amounts of functionality, it is vital thatdesigners have access to proven, up-to-date IP fromreliable sources.
上傳時間： 2013-11-15
上傳用戶：lyy1234
Prakash Rashinkar has over 15 years experience in system design and verificationof embedded systems for communication satellites, launch vehicles and spacecraftground systems, high-performance computing, switching, multimedia, and wirelessapplications. Prakash graduated with an MSEE from Regional Engineering College,Warangal, in India. He lead the team that was responsible for delivering themethodologies for SOC verification at Cadence Design Systems. Prakash is anactive member of the VSIA Functional Verification DWG. He is currently Architectin the Vertical Markets and Design Environments Group at Cadence.
上傳時間： 2014-01-24
上傳用戶：xinhaoshan2016
摘要: 串行傳輸技術具有更高的傳輸速率和更低的設計成本, 已成為業界首選, 被廣泛應用于高速通信領域。提出了一種新的高速串行傳輸接口的設計方案, 改進了Aurora 協議數據幀格式定義的弊端, 并采用高速串行收發器Rocket I/O, 實現數據率為2.5 Gbps的高速串行傳輸。關鍵詞: 高速串行傳輸; Rocket I/O; Aurora 協議 為促使FPGA 芯片與串行傳輸技術更好地結合以滿足市場需求, Xilinx 公司適時推出了內嵌高速串行收發器RocketI/O 的Virtex II Pro 系列FPGA 和可升級的小型鏈路層協議———Aurora 協議。Rocket I/O支持從622 Mbps 至3.125 Gbps的全雙工傳輸速率, 還具有8 B/10 B 編解碼、時鐘生成及恢復等功能, 可以理想地適用于芯片之間或背板的高速串行數據傳輸。Aurora 協議是為專有上層協議或行業標準的上層協議提供透明接口的第一款串行互連協議, 可用于高速線性通路之間的點到點串行數據傳輸, 同時其可擴展的帶寬, 為系統設計人員提供了所需要的靈活性[4]。但該協議幀格式的定義存在弊端,會導致系統資源的浪費。本文提出的設計方案可以改進Aurora 協議的固有缺陷,提高系統性能, 實現數據率為2.5 Gbps 的高速串行傳輸, 具有良好的可行性和廣闊的應用前景。
上傳時間： 2013-11-06
上傳用戶：smallfish
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
標簽： Transceiver Virtex Wizar GTP
上傳時間： 2013-10-23
上傳用戶：leyesome
在現代通信系統中，電話語音的頻帶被限制在300 Hz～4 kHz的范圍內，帶來了語音可懂度和自然度的降低。為了在不增加額外成本的前提下提高語音的可懂度和自然度，進行了電話語音頻帶擴展的研究。提出了一種改進的基于碼本映射的語音帶寬擴展算法：在碼本映射的過程中，使用加權系數來得到映射碼本。客觀測試結果表明，用此算法得到的寬帶語音的譜失真度比用一般的碼本映射降低至少2%。主觀測試結果表明，用此算法得到的寬帶語音具有更好的可懂度和自然度。 Abstract: In modern communication systems， the bandwidth of telephone speech is limited from 300Hz to 4 kHz， which reduces the intelligibility and naturalness of speech. Telephone speech bandwidth extension is researched to get wideband speech and to improve its intelligibility and naturalness， without increasing extra costs. This paper put forward an improved algorithm of speech bandwidth extension based on codebook mapping. In the process of codebook mapping， weighted coefficients were used to get mapping codebook. Objective tests show that spectral distortion of wideband speech obtained by this algorithm reduces at least 2%， comparing to conditional codebook mapping. Subjective tests show that the wideband speech obtained by this algorithm has better intelligibility and naturalness.
上傳時間： 2014-12-29
上傳用戶：15501536189
Abstract: Standard PCB design and mounting processes can adversely influence MEMS inertial sensors.This application note contains guidelines for the layout, soldering, and mounting of MEMS inertialsensors in LGA packages in order to reduce stresses and improve functionality.
上傳時間： 2014-01-15
上傳用戶：sjb555
Abstract: While many questions still surround the creation and deployment of the smart grid, the need for a reliablecommunications infrastructure is indisputable. Developers of the IEEE 1901.2 standard identified difficult channel conditionscharacteristic of low-frequency powerline communications and implemented an orthogonal frequency division multiplexing (OFDM)architecture using advanced modulation and channel-coding techniques. This strategy helped to ensure a robust communicationsnetwork for the smart grid.
上傳時間： 2013-10-18
上傳用戶：myworkpost
Abstract: This application note illustrates the flexibility of the MAX7060 ASK/FSK transmitter. While the currently available evaluationkit (EV kit) has been optimized for the device's use in a specific frequency band (i.e., 288MHz to 390MHz), this document addresseshow the EV kit circuitry can be modified for improved operation at 433.92MHz, a frequency commonly used in Europe. Twoalternative match and filter configurations are presented: one for optimizing drain efficiency, the other for achieving higher transmitpower. Features and capabilities of earlier Maxim industrial, scientific, and medical radio-frequency (ISM-RF) transmitters areprovided, allowing comparison of the MAX7060 to its predecessors. Several design guidelines and cautions for using the MAX7060are discussed.
上傳時間： 2013-11-14
上傳用戶：swaylong
Abstract: This application note discusses the development and deployment of 3G cellular femtocell base stations. The technicalchallenges for last-mile residential connectivity and adding system capacity in dense urban environments are discussed, with 3Gfemtocell base stations as a cost-effective solution. Maxim's 3GPP TS25.104-compliant transceiver solution is presented along withcomplete radio reference designs such as RD2550. For more information on the RD2550, see reference design 5364, "FemtocellRadio Reference Designs Using the MAX2550–MAX2553 Transceivers."
標簽： Base-Station Applications Single-Chip Transceiver
上傳時間： 2013-11-05
上傳用戶：超凡大師
In the past decade, the size and complexity of manyFPGA designs exceeds the time and resourcesavailable to most design teams, making the use andreuse of Intellectual Property (IP) imperative.However, integrating numerous IP blocks acquiredfrom both internal and external sources can be adaunting challenge that often extends, rather thanshortens, design time. As today's designs integrateincreasing amounts of functionality, it is vital thatdesigners have access to proven, up-to-date IP fromreliable sources.
上傳時間： 2013-11-11
上傳用戶：csgcd001
