16點(diǎn)FFT VHDL源程序，The xFFT16 fast Fourier transform (FFT) Core computes a 16-point complex FFT. The input data is a vector of 16 complex values represented as 16-bit 2’s complement numbers – 16-bits for each of the real and imaginary component of a datum.
上傳時(shí)間： 2013-12-20
上傳用戶：yph853211
The MIPS32® 4KEm™ core from MIPS® Technologies is a member of the MIPS32 4KE™ processor core family. It is a high-performance, low-power, 32-bit MIPS RISC core designed for custom system-on-silicon applications. The core is designed for semiconductor manufacturing companies, ASIC developers, and system OEMs who want to rapidly integrate their own custom logic and peripherals with a high-performance RISC processor. It is highly portable across processes, and can be easily integrated into full system-on-silicon designs, allowing developers to focus their attention on end-user products. The 4KEm core is ideally positioned to support new products for emerging segments of the digital consumer, network, systems, and information management markets, enabling new tailored solutions for embedded applications.
標(biāo)簽： MIPS 8482 Technologies 174
上傳時(shí)間： 2014-12-22
上傳用戶：semi1981
VHDL語言實(shí)現(xiàn)的穿行通訊，可實(shí)現(xiàn)閉環(huán)操作，通訊過程中每個(gè)bit位采樣3次，保證數(shù)據(jù)準(zhǔn)確。
上傳時(shí)間： 2014-01-13
上傳用戶：ynsnjs
DDR SDRAM控制器的VHDL源代碼，含詳細(xì)設(shè)計(jì)文檔。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上傳時(shí)間： 2014-11-01
上傳用戶：l254587896
軟件簡介：HI-TECH PICC 是一款高效的C編譯器，支持Microchip PICmicro 10/12/14/16/17系列控制器。是一款強(qiáng)勁的標(biāo)準(zhǔn)C編譯器，完全遵守ISO/ANSI C，支持所有的數(shù)據(jù)類型包括24 and 32 bit IEEE 標(biāo)準(zhǔn)浮點(diǎn)類型。智能優(yōu)化產(chǎn)生高質(zhì)量的代碼。屬于第三方開發(fā)工具。能和MPLAB整合，內(nèi)嵌開發(fā)環(huán)境（HI－TIDE）。 Hi-tech PICC Compiler v8.注冊(cè)碼 Serial: HCPIC-88888 First Name: ONE Last Name: TWO Company Name:ONE TWO Registration: 任意填，但一定要填 Activation: NPCBACMJKLPCADKLOEDBFPIOCIBAEIDI
標(biāo)簽： HI-TECH PICC 軟件 C編譯器
上傳時(shí)間： 2016-12-16
上傳用戶：Andy123456
H.264/AVC, the result of the collaboration between the ISO/IEC Moving Picture Experts Group and the ITU-T Video Coding Experts Group, is the latest standard for video coding. The goals of this standardization effort were enhanced compression efficiency, network friendly video representation for interactive (video telephony) and non-interactive applications (broadcast, streaming, storage, video on demand). H.264/AVC provides gains in compression efficiency of up to 50％ over a wide range of bit rates and video resolutions compared to previous standards. Compared to previous standards, the decoder complexity is about four times that of MPEG-2 and two times that of MPEG-4 Visual Simple Profile. This paper provides an overview of the new tools, features and complexity of H.264/AVC.
標(biāo)簽： the collaboration between Experts
上傳時(shí)間： 2013-12-30
上傳用戶：dongbaobao
*** *** *** *** *** *** ***** ** Two wire/I2C Bus READ/WRITE Sample Routines of Microchip s ** 24Cxx / 85Cxx serial CMOS EEPROM interfacing to a ** PIC16C54 8-bit CMOS single chip microcomputer ** Revsied Version 2.0 (4/2/92). ** ** Part use = PIC16C54-XT/JW ** Note: 1) All timings are based on a reference crystal frequency of 2MHz ** which is equivalent to an instruction cycle time of 2 usec. ** 2) Address and literal values are read in octal unless otherwise ** specified.
標(biāo)簽： Microchip Routines Sample WRITE
上傳時(shí)間： 2013-12-27
上傳用戶：ljmwh2000
selects the mux channel and configures the MAX197 for second write pulse, written with ACQMOD = 0, termi- either unipolar or bipolar input range. A write pulse (WR nates acquisition and starts conversion on WR°Os risin + CS) can either start an acquisition interval or initiate a edge (Figure 6). However, if the second control byte combined acquisition plus conversion. The sampling contains ACQMOD = 1, an indefinite acquisition interval interval occurs at the end of the acquisition interval. is restarted. The ACQMOD bit in the input control byte offer
標(biāo)簽： configures the selects channel
上傳時(shí)間： 2013-12-09
上傳用戶：
selects the mux channel and configures the MAX197 for second write pulse, written with ACQMOD = 0, termi- either unipolar or bipolar input range. A write pulse (WR nates acquisition and starts conversion on WR°Os risin + CS) can either start an acquisition interval or initiate a edge (Figure 6). However, if the second control byte combined acquisition plus conversion. The sampling contains ACQMOD = 1, an indefinite acquisition interval interval occurs at the end of the acquisition interval. is restarted. The ACQMOD bit in the input control byte offer
標(biāo)簽： configures the selects channel
上傳時(shí)間： 2016-12-24
上傳用戶：朗朗乾坤
selects the mux channel and configures the MAX197 for second write pulse, written with ACQMOD = 0, termi- either unipolar or bipolar input range. A write pulse (WR nates acquisition and starts conversion on WR°Os risin is restarted. The ACQMOD bit in the input control byte offer+ CS) can either start an acquisition interval or initiate a edge (Figure 6). However, if the second control byte combined acquisition plus conversion. The sampling contains ACQMOD = 1, an indefinite acquisition interval interval occurs at the end of the acquisition interval.
標(biāo)簽： configures the selects channel
上傳時(shí)間： 2016-12-24
上傳用戶：yzhl1988
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