The #1 Step-by-Step Guide to labviewNow Completely Updated for labview 8!
Master labview 8 with the industry's friendliest, most intuitive tutorial: labview for Everyone, Third Edition. Top labview experts Jeffrey Travis and Jim Kring teach labview the easy way: through carefully explained, step-by-step examples that give you reusable code for your own projects!
This brand-new Third Edition has been fully revamped and expanded to reflect new features and techniques introduced in labview 8. You'll find two new chapters, plus dozens of new topics, including Project Explorer, AutoTool, XML, event-driven programming, error handling, regular expressions, polymorphic VIs, timed structures, advanced reporting, and much more. Certified labview Developer (CLD) candidates will find callouts linking to key objectives on NI's newest exam, making this book a more valuable study tool than ever.
Not just what to d why to do it!
Use labview to build your own virtual workbench
Master labview's foundations: wiring, creating, editing, and debugging VIs; using controls and indicators; working with data structures; and much more
Learn the "art" and best practices of effective labview development
NEW: Streamline development with labview Express VIs
NEW: Acquire data with NI-DAQmx and the labview DAQmx VIs
NEW: Discover design patterns for error handling, control structures, state machines, queued messaging, and more
NEW: Create sophisticated user interfaces with tree and tab controls, drag and drop, subpanels, and more
Whatever your application, whatever your role, whether you've used labview or not, labview for Everyone, Third Edition is the fastest, easiest way to get the results you're after!
標(biāo)簽：
Everyone
LabVIEW
for
英文
上傳時(shí)間：
2013-10-14
上傳用戶：shawvi
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html
Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture
The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications.
The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation.
Some of the UltraScale architecture breakthroughs include:
• Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50%
• Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability
• Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization
• 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard
• Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets
• Greatly enhanced DSP and packet handling
The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽：
UltraScale
Xilinx
架構(gòu)
上傳時(shí)間：
2013-11-21
上傳用戶：wxqman
