FPGA-CPld芯片設(shè)置方法
上傳時(shí)間： 2015-01-01
上傳用戶：luopoguixiong
FPGA與CPld區(qū)別
上傳時(shí)間： 2013-10-25
上傳用戶：qw12
CPld最小系統(tǒng)設(shè)計(jì)
標(biāo)簽： CPld 最小系統(tǒng) 原理圖
上傳時(shí)間： 2013-12-23
上傳用戶：410805624
CPld開發(fā)套件光盤說(shuō)明
上傳時(shí)間： 2013-10-24
上傳用戶：hfmm633
Most designers wish to utilize as much of a device as possible in order to enhance the overallproduct performance, or extend a feature set. As a design grows, inevitably it will exceed thearchitectural limitations of the device. Exactly why a design does not fit can sometimes bedifficult to determine. Programmable logic devices can be configured in almost an infinitenumber of ways. The same design may fit when you use certain implementation switches, andfail to fit when using other switches. This application note attempts to clarify the CPld softwareimplementation (CPldFit) options, as well as discuss implementation tips in CoolRunnerTM-IIdesigns in order to maximize CPld utilization.
上傳時(shí)間： 2014-01-11
上傳用戶：a471778
This introduction covers the fundamentals of VHDL as applied to Complex ProgrammableLogic Devices (CPlds). Specifically included are those design practices that translate soundlyto CPlds, permitting designers to use the best features of this powerful language to extractoptimum performance for CPld designs.
上傳時(shí)間： 2013-11-21
上傳用戶：gtf1207
This application note provides a functional description of VHDL source code for a N x N DigitalCrosspoint Switch. The code is designed with eight inputs and eight outputs in order to targetthe 128-macrocell CoolRunner™-II CPld device but can be easily expanded to target higherdensity devices. To obtain the VHDL source code described in this document, go to sectionVHDL Code, page 5 for instructions.
標(biāo)簽： CoolRunner-II XAPP CPld 380
上傳時(shí)間： 2013-10-26
上傳用戶：kiklkook
The CoolRunner-II CPld is a highly uniform family of fast, low-power devices. Theunderlying architecture is a traditional CPld architecture, combining macrocells intofunction blocks interconnected with a global routing matrix, the Xilinx AdvancedInterconnect Matrix (AIM). The function blocks use a PLA configuration that allowsall product terms to be routed and shared among any of the macrocells of the functionblock.
上傳時(shí)間： 2013-11-03
上傳用戶：1037540470
This application note shows how a Xilinx CoolRunnerTM-II CPld can be used as a simplelogical switch that can quickly and reliably select between different MPEG video sources. Thesource code for the design is available on the Xilinx website, and is linked from the “VHDLCode” section. The code can be expanded by the user to perform additional operations usingthe remaining CPld resources
標(biāo)簽： CoolRunner-II Xilinx XAPP CPld
上傳時(shí)間： 2013-12-16
上傳用戶：qwer0574
利用一塊芯片完成除時(shí)鐘源、按鍵、揚(yáng)聲器和顯示器（數(shù)碼管）之外的所有數(shù)字電路功能。所有數(shù)字邏輯功能都在CPld器件上用VHDL語(yǔ)言實(shí)現(xiàn)。這樣設(shè)計(jì)具有體積小、設(shè)計(jì)周期短（設(shè)計(jì)過(guò)程中即可實(shí)現(xiàn)時(shí)序仿真）、調(diào)試方便、故障率低、修改升級(jí)容易等特點(diǎn)。 本設(shè)計(jì)采用自頂向下、混合輸入方式（原理圖輸入—頂層文件連接和VHDL語(yǔ)言輸入—各模塊程序設(shè)計(jì)）實(shí)現(xiàn)數(shù)字鐘的設(shè)計(jì)、下載和調(diào)試。
標(biāo)簽： CPld VHDL 語(yǔ)言 數(shù)字
上傳時(shí)間： 2013-10-24
上傳用戶：古谷仁美
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