飛思卡爾智能車的舵機(jī)測(cè)試程序 #include <hidef.h> /* common defines and macros */#include <MC9S12XS128.h> /* derivative information */#pragma LINK_INFO DERIVATIVE "mc9s12xs128" void SetBusCLK_16M(void) { CLKSEL=0X00; PLLCTL_PLLON=1; //鎖相環(huán)電路允許位 SYNR=0x00 | 0x01; //SYNR=1 REFDV=0x80 | 0x01; POSTDIV=0x00; _asm(nop); _asm(nop); while(!(CRGFLG_LOCK==1)); CLKSEL_PLLSEL =1; } void PWM_01(void) { //舵機(jī)初始化 PWMCTL_CON01=1; //0和1聯(lián)合成16位PWM； PWMCAE_CAE1=0; //選擇輸出模式為左對(duì)齊輸出模式 PWMCNT01 = 0; //計(jì)數(shù)器清零； PWMPOL_PPOL1=1; //先輸出高電平，計(jì)數(shù)到DTY時(shí)，反轉(zhuǎn)電平 PWMPRCLK = 0X40; //clockA 不分頻,clockA=busclock=16MHz;CLK B 16分頻:1Mhz PWMSCLA = 0x08; //對(duì)clock SA 16分頻,pwm clock=clockA/16=1MHz; PWMCLK_PCLK1 = 1; //選擇clock SA做時(shí)鐘源 PWMPER01 = 20000; //周期20ms； 50Hz; PWMDTY01 = 1500; //高電平時(shí)間為1.5ms; PWME_PWME1 = 1;
標(biāo)簽： 飛思卡爾智能車 舵機(jī) 測(cè)試程序
上傳時(shí)間： 2013-11-04
上傳用戶：狗日的日子
This example provides a description of how to use the USART with hardware flowcontrol and communicate with the Hyperterminal.First, the USART2 sends the TxBuffer to the hyperterminal and still waiting fora string from the hyperterminal that you must enter which must end by '\r'character (keypad ENTER button). Each byte received is retransmitted to theHyperterminal. The string that you have entered is stored in the RxBuffer array. The receivebuffer have a RxBufferSize bytes as maximum. The USART2 is configured as follow: - BaudRate = 115200 baud - Word Length = 8 Bits - One Stop Bit - No parity - Hardware flow control enabled (RTS and CTS signals) - Receive and transmit enabled - USART Clock disabled - USART CPOL: Clock is active low - USART CPHA: Data is captured on the second edge - USART LastBit: The clock pulse of the last data bit is not output to the SCLK pin
上傳時(shí)間： 2013-10-31
上傳用戶：yy_cn
資料介紹說明 orcad到power格式Dxdesigner轉(zhuǎn)換器下載，為綠色免安裝版，下載后雙擊schcvt.exe，即可使用了，界面如下圖所示
標(biāo)簽： Dxdesigner orcad power 轉(zhuǎn)換器
上傳時(shí)間： 2013-11-01
上傳用戶：xinyuzhiqiwuwu
Abstract: Using a wafer-level package (WLP) can reduce the overall size and cost of your solution.However when using a WLP IC, the printed circuit board (PCB) layout can become more complex and, ifnot carefully planned, result in an unreliable design. This article presents some PCB designconsiderations and general recommendations for choosing a 0.4mm- or 0.5mm-pitch WLP for yourapplication.
標(biāo)簽： Considerations Guidelines and Design
上傳時(shí)間： 2013-11-09
上傳用戶：ls530720646
As businesses and consumers expect more fromportable electronics, the FPGA industry has beencompelled to re-think how it serves these low-power,cost-sensitive markets. Application classes like
上傳時(shí)間： 2013-11-08
上傳用戶：immanuel2006
PADS-PowerLogic and PowerPcb實(shí)用教程
標(biāo)簽： PADS-PowerLogic PowerPcb and 實(shí)用教程
上傳時(shí)間： 2014-01-24
上傳用戶：qiaoyue
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System
標(biāo)簽： FPGA 安全系統(tǒng)
上傳時(shí)間： 2013-11-14
上傳用戶：zoudejile
Abstract: This reference design explains how to power the Xilinx Zynq Extensible Processing Platform (EPP) and peripheral ICs using
標(biāo)簽： Xilinx Zynq EPP 擴(kuò)展式
上傳時(shí)間： 2013-10-13
上傳用戶：peterli123456
Applying power to a standard logic chip, SRAM, or EPROM, usually results in output pinstracking the applied voltage as it rises. Programmable logic attempts to emulate that behavior,but physics forbids perfect emulation, due to the device programmability. It requires care tospecify the pin behavior, because programmable parts encounter unknown variables – yourdesign and your power environment.
標(biāo)簽： Xilinx XAPP CPLD 440
上傳時(shí)間： 2013-11-24
上傳用戶：253189838
Today’s digital systems combine a myriad of chips with different voltage configurations.Designers must interface 2.5V processors with 3.3V memories—both RAM and ROM—as wellas 5V buses and multiple peripheral chips. Each chip has specific power supply needs. CPLDsare ideal for handling the multi-voltage interfacing, but do require forethought to ensure correctoperation.
上傳時(shí)間： 2013-11-10
上傳用戶：yy_cn
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