All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the Current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
上傳時間： 2013-10-23
上傳用戶：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the Current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上傳時間： 2014-04-02
上傳用戶：han_zh
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their productsor to discontinue any product or service without notice, and advise customers to obtain the latestversion of relevant information to verify, before placing orders, that information being relied onis Current and complete. All products are sold subject to the terms and conditions of sale suppliedat the time of order acknowledgement, including those pertaining to warranty, patentinfringement, and limitation of liability
上傳時間： 2013-12-26
上傳用戶：凌云御清風
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the Current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-13
上傳用戶：瓦力瓦力hong
特點 最高輸入頻率 10KHz 顯示范圍0-9999（一段設定）0至999999累積量 計數速度 50/10000脈波/秒可選擇 輸入脈波具有預設刻度功能 累積量同步（批量）或非同步（批次）計數可選擇 數位化指撥設定操作簡易 計數暫時停止功能 1組報警功能 2:主要規格 脈波輸入型式: Jump-pin selectable Current sourcing(NPN) or Current sinking (PNP) 脈波觸發電位: HI bias (CMOS) (VIH=7.5V, VIL=5.5V) LO bias (TTL) (VIH=3.7V, VIL=2.0V) 最高輸入頻率: <10KHz (up,down,up/down mode) 輸出動作時間 : 0.1 to 99.9 second adjustable 輸出復歸方式: Manual(N) or automatic (R or C) can be modif 繼電器容量: AC 250V-5A, DC 30V-7A 顯示值范圍: 0-9999（PV,SV） 0-999999(TV) 顯示幕: Red high efficiency LEDs high 7.0mm (.276")(PV,SV) Red high efficiency LEDs high 9.2mm (.36")(TV) 參數設定方式: Touch switches 感應器電源: 12VDC +/-3%(<60mA) 記憶方式: Non-volatile E2PROM memory 絕緣耐壓能力: 2KVac/1 min. (input/output/power) 1600Vdc (input/output) 使用環境條件: 0-50℃(20 to 90% RH non-condensed) 存放環境條件: 0-70℃(20 to 90% RH non-condensed) CE認證: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
上傳時間： 2013-10-24
上傳用戶：wvbxj
特點 顯示值范圍-199999至999999位數 最高輸入頻率 5KHz 90度相位差加減算具有提高解析度4倍功能 輸入脈波具有預設刻度功能 定位基準值可任意設定 比較磁滯值可任意設定 數位化指撥設定操作簡易 3組繼電器輸出功能 2:主要規格 脈波輸入型式: Jump-pin selectable Current sourcing(NPN) or Current sinking (PNP) 脈波觸發電位: HI bias (CMOS) (VIH=7.5V, VIL=5.5V) LO bias (TTL) (VIH=3.7V, VIL=2.0V) 最高輸入頻率: <5KHz 定位置范圍: -199999 to 999999 second adjustabl 比較磁滯范圍: 0 to 9999 adjustable 繼電器容量: AC 250V-5A, DC 30V-7A 顯示值范圍: -199999 to 999999 顯示幕: Red high efficiency LEDs high 9.2mm (.36") 參數設定方式: Touch switches 感應器電源: 12VDC +/-3%(<60mA) 記憶方式: Non-volatile E2PROM memory 絕緣耐壓能力: 2KVac/1 min. (input/output/power) 1600Vdc (input/output) 使用環境條件: 0-50℃(20 to 90% RH non-condensed) 存放環境條件: 0-70℃(20 to 90% RH non-condensed) CE認證: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
上傳時間： 2014-12-03
上傳用戶：xjz632
特點 精確度0.25%滿刻度 ±1位數 輸入配線系統可任意選擇 CT比可任意設定 具有異常電流值與異常次數記錄保留功能 電流過高或過低檢測可任意設定 報警繼電器復歸方式可任意設定 尺寸小,穩定性高 2.主要規格 輔助電源: AC110V&220V ±20%(50 or 60Hz) AC220V&440V ±20%(50 or 60Hz)(optional) 精確度: 0.25% F.S. ±1 digit 輸入負載: <0.2VA (Current) 最大過載能力 : Current related input: 2 x rated continuous 10 x rated 30 sec. 25 x rated 3sec. 50 x rated 1 sec. 輸入電流范圍: AC0-5A (10-1000Hz) CT ratio : 1-2000 adjustable 啟動延遲動作時間: 0-99.9 second adjustable 繼電器延遲動作時間: 0-99.9 second adjustable 繼電器復歸方式: Manual (N) / latch(L) can be modified 繼電器磁滯范圍: 0-999 digit adjustable 繼電器動作方向: HI /LO/GO/HL can be modified 繼電器容量: AC 250V-5A, DC 30V-7A 過載顯示: "doFL" 溫度系數: 50ppm/℃ (0-50℃) 顯示幕: Red high efficiency LEDs high 14.22mm(.56")(PV) Red high efficiency LEDs high 14.22mm(.276")(NO) 參數設定方式: Touch switches 記憶型式 : Non-volatile E2PROM memory 絕緣耐壓能力: 2KVac/1 min. (input/output/power) 1600Vdc(input/output 使用環境條件 : 0-50℃(20 to 90% RH non-condensed) 存放環境條件: 0-70℃(20 to 90% RH non-condensed) CE認證: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
上傳時間： 2013-10-14
上傳用戶：wanghui2438
特點 最高輸入頻率 10KHz 計數速度 50/10000脈波/秒可選擇 四種輸入模式可選擇(加算,減算,加減算,90度相位差加減算) 90度相位差加減算具有提高解析度4倍功能 輸入脈波具有預設刻度功能 計數暫時停止功能 3組報警功能 15BIT類比輸出功能 數位RS-485界面 2:主要規格 脈波輸入型式: Jump-pin selectable Current sourcing(NPN) or Current sinking (PNP) 脈波觸發電位: HI bias (CMOS) (VIH=7.5V, VIL=5.5V) LO bias (TTL) (VIH=3.7V, VIL=2.0V) 最高輸入頻率: <10KHz (up,down,up/down mode) <3KHz (quadrature mode) 輸出動作時間 : 0.1 to 99.9 second adjustable 輸出復歸方式: Manual(N) or automatic (R or C) can be modif 繼電器容量: AC 250V-5A, DC 30V-7A 顯示值范圍: -199999 to 999999 類比輸出解析度: 15 bit DAC 輸出反應速度: < 1/f+10ms(0-90%) 輸出負載能力: < 10mA for voltage mode < 10V for Current mode <[(V+)-7.5V]/20mA for two-wire mode 輸出之漣波: < 0.1% F.S. 通訊位址: "01"-"FF" 傳輸速度: 19200/9600/4800/2400 selective 通信協議: Modbus RTU mode 顯示幕: Red high efficiency LEDs high 14.22mm (.56") 參數設定方式: Touch switches 感應器電源: 12VDC +/-3%(<60mA) 記憶方式: Non-volatile E2PROM memory 絕緣耐壓能力: 2KVac/1 min. (input/output/power) 1600Vdc (input/output) 使用環境條件: 0-50℃(20 to 90% RH non-condensed) 存放環境條件: 0-70℃(20 to 90% RH non-condensed) CE認證: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
上傳時間： 2013-11-23
上傳用戶：redmoons
特點 最高輸入頻率 10KHz 計數速度 50/10000脈波/秒可選擇 四種輸入模式可選擇(加算,減算,加減算,90度相位差加減算) 90度相位差加減算具有提高解析度4倍功能 輸入脈波具有預設刻度功能 前置量設定功能(二段設定)可選擇 數位化指撥設定操作簡易 計數暫時停止功能 3組報警功能 2:主要規格 脈波輸入型式: Jump-pin selectable Current sourcing(NPN) or Current sinking (PNP) 脈波觸發電位: HI bias (CMOS) (VIH=7.5V, VIL=5.5V) LO bias (TTL) (VIH=3.7V, VIL=2.0V) 最高輸入頻率: <10KHz (up,down,up/down mode) <5KHz (quadrature mode) 輸出動作時間 : 0.1 to 99.9 second adjustable 輸出復歸方式: Manual(N) or automatic (R or C) can be modif 繼電器容量: AC 250V-5A, DC 30V-7A 顯示值范圍: -199999 to 999999 顯示幕: Red high efficiency LEDs high 9.2mm (.36") 參數設定方式: Touch switches 感應器電源: 12VDC +/-3%(<60mA) ( 感應器電源 ) 記憶方式: Non-volatile E2PROM memory 絕緣耐壓能力: 2KVac/1 min. (input/output/power) 1600Vdc (input/output) 使用環境條件: 0-50℃(20 to 90% RH non-condensed) 存放環境條件: 0-70℃(20 to 90% RH non-condensed) CE認證: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
上傳時間： 2013-11-12
上傳用戶：909000580
特點 精確度0.1%滿刻度 可輸入交直流電流/交直流電壓/電位計/傳送器...等信號 16 BIT類比輸出功能 輸入與輸出絕緣耐壓2仟伏特/1分鐘 寬范圍交直流兩用電源設計 尺寸小,穩定性高 2主要規格 精確度: 0.1% F.S. (23 ±5℃) 顯示值范圍: 0-±19999 digit adjustable 類比輸出解析度: 16 bit DAC 輸出反應速度: < 250 ms (0-90%)(>10Hz) 輸出負載能力: < 10mA for voltage mode < 10V for Current mode 輸出之漣波: < 0.1% F.S. 歸零調整范圍: 0- ±9999 Digit adjustable 最大值調整范圍: 0- ±9999 Digit adjustable 溫度系數: 50ppm/℃ (0-50℃) 顯示幕: Red high efficiency LEDs high 10.16mm (0.4") 隔離特性: Input/Output/Power/Case 參數設定方式: Touch switches 記憶方式: Non-volatile E2PROM memory 絕緣抗阻: >100Mohm with 500V DC 絕緣耐壓能力: 2KVac/1 min. (input/output/power) 1600Vdc (input/output) 使用環境條件: 0-60℃(20 to 90% RH non-condensed) 存放環境條件: 0-70℃(20 to 90% RH non-condensed) 安裝方式: Socket/plugin type with barrier terminals CE認證: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
上傳時間： 2014-01-05
上傳用戶：eastgan
