The UMTS Physical Layer model consists of an end-to-end (transmitter-to-receiver) simulation of the Frequency Division Duplex (FDD) Downlink physical layer for several Dedicated Channels (DCH) as specified by the 3GPP standard (Release 99).
標(biāo)簽： transmitter-to-receiver end-to-end simulation Physical
上傳時(shí)間： 2014-01-11
上傳用戶：it男一枚
Algorithms for VLSI Physical Design Automation, 3E
標(biāo)簽： Algorithms Automation Physical Design VLSI for 3E
上傳時(shí)間： 2018-03-14
上傳用戶：sjjoe
The Internet of Things is considered to be the next big opportunity, and challenge, for the Internet engineering community, users of technology, companies and society as a whole. It involves connecting embedded devices such as sensors, home appliances, weather stations and even toys to Internet Protocol (IP) based networks. The number of IP-enabled embedded devices is increasing rapidly, and although hard to estimate, will surely outnumber the number of personal computers (PCs) and servers in the future. With the advances made over the past decade in microcontroller,low-power radio, battery and microelectronic technology, the trend in the industry is for smart embedded devices (called smart objects) to become IP-enabled, and an integral part of the latest services on the Internet. These services are no longer cyber, just including data created by humans, but are to become very connected to the physical world around us by including sensor data, the monitoring and control of machines, and other kinds of physical context. We call this latest frontier of the Internet, consisting of wireless low-power embedded devices, the Wireless Embedded Internet. Applications that this new frontier of the Internet enable are critical to the sustainability, efficiency and safety of society and include home and building automation, healthcare, energy efficiency, smart grids and environmental monitoring to name just a few.
標(biāo)簽： Embedded Internet Wireless 6LoWPAN The
上傳時(shí)間： 2020-05-26
上傳用戶：shancjb
The ever-increasing demand for private and sensitive data transmission over wireless net- works has made security a crucial concern in the current and future large-scale, dynamic, and heterogeneous wireless communication systems. To address this challenge, computer scientists and engineers have tried hard to continuously come up with improved crypto- graphic algorithms. But typically we do not need to wait too long to find an efficient way to crack these algorithms. With the rapid progress of computational devices, the current cryptographic methods are already becoming more unreliable. In recent years, wireless re- searchers have sought a new security paradigm termed physical layer security. Unlike the traditional cryptographic approach which ignores the effect of the wireless medium, physi- cal layer security exploits the important characteristics of wireless channel, such as fading, interference, and noise, for improving the communication security against eavesdropping attacks. This new security paradigm is expected to complement and significantly increase the overall communication security of future wireless networks.
標(biāo)簽： Communications Physical Security Wireless Layer in
上傳時(shí)間： 2020-05-31
上傳用戶：shancjb
新一代FPGA綜合技術(shù),邏輯設(shè)計(jì)中出現(xiàn)的多個(gè)層次進(jìn)行優(yōu)化， 通過精簡邏輯層次，提升了電路性能，并且降低了功耗
標(biāo)簽： Precision Physical 2010 2180
上傳時(shí)間： 2013-06-12
上傳用戶：jlyaccounts
·Advanced ASIC Chip Synthesis Using Synopsys Design Compiler,Physical Compiler and Primetime
標(biāo)簽： nbsp Synthesis Advanced Synopsys
上傳時(shí)間： 2013-04-24
上傳用戶：alia
Sensors for pressure, load, temperature, acceleration andmany other physical quantities often take the form of aWheatstone bridge. These sensors can be extremely linearand stable over time and temperature. However, mostthings in nature are only linear if you don’t bend them toomuch. In the case of a load cell, Hooke’s law states that thestrain in a material is proportional to the applied stress—as long as the stress is nowhere near the material’s yieldpoint (the “point of no return” where the material ispermanently deformed).
標(biāo)簽： Delta Sigma ADC 測(cè)量技術(shù)
上傳時(shí)間： 2013-11-13
上傳用戶：墻角有棵樹
This document provides practical, common guidelines for incorporating PCI Express interconnect layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10- layer or more server baseboard designs. Guidelines and constraints in this document are intended for use on both baseboard and add-in card PCB designs. This includes interconnects between PCI Express devices located on the same baseboard (chip-to-chip routing) and interconnects between a PCI Express device located “down” on the baseboard and a device located “up” on an add-in card attached through a connector. This document is intended to cover all major components of the physical interconnect including design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card edge-finger and connector considerations. The intent of the guidelines and examples is to help ensure that good high-speed signal design practices are used and that the timing/jitter and loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect. However, while general physical guidelines and suggestions are given, they may not necessarily guarantee adequate performance of the interconnect for all layouts and implementations. Therefore, designers should consider modeling and simulation of the interconnect in order to ensure compliance to all applicable specifications. The document is composed of two main sections. The first section provides an overview of general topology and interconnect guidelines. The second section concentrates on physical layout constraints where bulleted items at the beginning of a topic highlight important constraints, while the narrative that follows offers additional insight.
標(biāo)簽： pci PCB 設(shè)計(jì)規(guī)范
上傳時(shí)間： 2013-10-15
上傳用戶：busterman
Abstract: Stuxnet, a sophisticated virus that damaged Iran's nuclear capability, should be an eye openerfor the world. We can choose to learn something very narrow (how to combat the Stuxnet virus) or wecan choose to focus on the larger goal of thwarting the next type of creative cyber attack. Unfortunately,critical industrial infrastructure is not currently designed with security as a key goal, leaving open multipleavenues for an educated and funded attacker to create massive problems. This tutorial outlines somebasic concepts that engineers and product definers should consider to make sure their new projects stayahead of future threats.
標(biāo)簽： 智能電網(wǎng) 安全保護(hù)
上傳時(shí)間： 2013-11-17
上傳用戶：llwap
SDRAM的原理和時(shí)序 SDRAM內(nèi)存模組與基本結(jié)構(gòu) 我們平時(shí)看到的SDRAM都是以模組形式出現(xiàn)，為什么要做成這種形式呢？這首先要接觸到兩個(gè)概念：物理Bank與芯片位寬。1、 物理Bank 傳統(tǒng)內(nèi)存系統(tǒng)為了保證CPU的正常工作，必須一次傳輸完CPU在一個(gè)傳輸周期內(nèi)所需要的數(shù)據(jù)。而CPU在一個(gè)傳輸周期能接受的數(shù) 據(jù)容量就是CPU數(shù)據(jù)總線的位寬，單位是bit（位）。當(dāng)時(shí)控制內(nèi)存與CPU之間數(shù)據(jù)交換的北橋芯片也因此將內(nèi)存總線的數(shù)據(jù)位寬 等同于CPU數(shù)據(jù)總線的位寬，而這個(gè)位寬就稱之為物理Bank（Physical Bank，下文簡稱P-Bank）的位寬。所以，那時(shí)的內(nèi)存必須要組織成P-Bank來與CPU打交道。資格稍老的玩家應(yīng)該還記 得Pentium剛上市時(shí)，需要兩條72pin的SIMM才能啟動(dòng)，因?yàn)橐粭l72pin -SIMM只能提供32bit的位寬，不能滿足Pentium的64bit數(shù)據(jù)總線的需要。直到168pin-SDRAM DIMM上市后，才可以使用一條內(nèi)存開機(jī)。不過要強(qiáng)調(diào)一點(diǎn)，P-Bank是SDRAM及以前傳統(tǒng)內(nèi)存家族的特有概念，RDRAM中將以通道（Channel）取代，而對(duì) 于像Intel E7500那樣的并發(fā)式多通道DDR系統(tǒng)，傳統(tǒng)的P-Bank概念也不適用。2、 芯片位寬 上文已經(jīng)講到SDRAM內(nèi)存系統(tǒng)必須要組成一個(gè)P-Bank的位寬，才能使CPU正常工作，那么這個(gè)P-Bank位寬怎么得到呢 ？這就涉及到了內(nèi)存芯片的結(jié)構(gòu)。 每個(gè)內(nèi)存芯片也有自己的位寬，即每個(gè)傳輸周期能提供的數(shù)據(jù)量。理論上，完全可以做出一個(gè)位寬為64bit的芯片來滿足P-Ban k的需要，但這對(duì)技術(shù)的要求很高，在成本和實(shí)用性方面也都處于劣勢(shì)。所以芯片的位寬一般都較小。臺(tái)式機(jī)市場(chǎng)所用的SDRAM芯片 位寬最高也就是16bit，常見的則是8bit。這樣，為了組成P-Bank所需的位寬，就需要多顆芯片并聯(lián)工作。對(duì)于16bi t芯片，需要4顆（4×16bit=64bit）。對(duì)于8bit芯片，則就需要8顆了。以上就是芯片位寬、芯片數(shù)量與P-Bank的關(guān)系。P-Bank其實(shí)就是一組內(nèi)存芯片的集合，這個(gè)集合的容量不限，但這個(gè)集合的 總位寬必須與CPU數(shù)據(jù)位寬相符。隨著計(jì)算機(jī)應(yīng)用的發(fā)展，
上傳時(shí)間： 2013-11-04
上傳用戶：zhuimenghuadie
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