TAD10023 Demodulator From NXP.CU1216 is tuner.
標(biāo)簽： Demodulator 10023 tuner 1216
上傳時(shí)間： 2014-01-18
上傳用戶：13215175592
receiver matlab Demodulator
標(biāo)簽： Demodulator receiver matlab
上傳時(shí)間： 2014-12-22
上傳用戶：zaizaibang
QAM 4 Modulator and Demodulator based on ETSI TETRA Standard
標(biāo)簽： Demodulator Modulator Standard TETRA
上傳時(shí)間： 2017-07-24
上傳用戶：xfbs821
Designing read/write device (RWD) units for industrial RF-Identification applications is strongly facilitated by the NXP Semiconductors HITAG Reader Chip HTRC110. All needed function blocks, like the antenna driver, modulator Demodulator and antenna diagnosis unit, are integrated in the HTRC110. Therefore only a minimum number of additional passive components are required for a complete RWD. This Application Note describes how to design an industrial RF-Identification system with the HTRC110. The major focus is dimensioning of the antenna, all other external components including clock and power supply, as well as the demodulation principle and its implementatio
上傳時(shí)間： 2013-10-22
上傳用戶：zhengjian
為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對(duì)移相（QDPSK)信號(hào)調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計(jì)了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺(tái)上，進(jìn)行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測(cè)試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達(dá)到了預(yù)期的設(shè)計(jì)要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the Demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標(biāo)簽： QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計(jì)
上傳時(shí)間： 2014-01-13
上傳用戶：qoovoop
為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對(duì)移相（QDPSK)信號(hào)調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計(jì)了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺(tái)上，進(jìn)行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測(cè)試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達(dá)到了預(yù)期的設(shè)計(jì)要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the Demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標(biāo)簽： QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計(jì)
上傳時(shí)間： 2013-10-28
上傳用戶：jyycc
This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static channel and AWGN noise. The packet include: 1) Packet Builder (Viterbi Encoding, Interleaver, PN generation) 2) Modulator (RRC filter) 3) Demodulator (Matched Filter, RAKE receiver) 4) Receiver (HD or SD) (Deinterleaver, Viterbi Decoder). You should run "Simulation.m" function that include all modules.
標(biāo)簽： simulation baseband channel packet
上傳時(shí)間： 2014-11-09
上傳用戶：hwl453472107
his packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static channel and AWGN noise. The packet include: 1) Packet Builder (Viterbi Encoding, Interleaver, PN generation) 2) Modulator (RRC filter) 3) Demodulator (Matched Filter, RAKE receiver) 4) Receiver (HD or SD) (Deinterleaver, Viterbi Decoder). You should run "Simulation.m" function that include all modules.
標(biāo)簽： simulation baseband channel packet
上傳時(shí)間： 2013-12-23
上傳用戶：zhangyigenius
This paper investigates the design of joint frequency offset and carrier phase estimation of a multi-frequency time division multiple access (MF-TDMA) Demodulator that is applied to a digital video broadcasting—return channel system via satellite (DVB-RCS). The proposed joint estimation algorithm is based on the interpolation technique for two correlation values in the frequency and phase domains. This simple interpolation technique can significantly improve frequency and phase resolution capabilities of the proposed technique without increasing the number of the correlation values. In addition, the overall block diagram of a digital communications receiver for DVB-RCS is presented, which was designed using the proposed estimation algorithms. Index Terms—Carrier phase estimation, DVB-RCS, frequency offset estimation, interpolation, joint estimation, MF-TDMA.
標(biāo)簽： investigates estimation frequency carrier
上傳時(shí)間： 2015-12-30
上傳用戶：ls530720646
This packet is a IS-95 baseband simulation for 1 data channel of 9.6 KBps rate. The simulation is written for static channel and AWGN noise. The packet include: 1) Packet Builder (Viterbi Encoding, Interleaver, PN generation) 2) Modulator (RRC filter) 3) Demodulator (Matched Filter, RAKE receiver) 4) Receiver (HD or SD) (Deinterleaver, Viterbi Decoder).
標(biāo)簽： simulation baseband channel packet
上傳時(shí)間： 2014-12-20
上傳用戶：ukuk
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