針對使用硬件描述語言進(jìn)行設(shè)計(jì)存在的問題，提出一種基于FPGA并采用DSP Builder作為設(shè)計(jì)工具的數(shù)字信號處理器設(shè)計(jì)方法。并按照Matlab/Simulink/DSP Builder/QuartusⅡ設(shè)計(jì)流程，設(shè)計(jì)了一個(gè)12階FIR 低通數(shù)字濾波器，通過Quartus 時(shí)序仿真及嵌入式邏輯分析儀SignalTapⅡ硬件測試對設(shè)計(jì)進(jìn)行了驗(yàn)證。結(jié)果表明，所設(shè)計(jì)的FIR 濾波器功能正確，性能良好。 Abstract: Aiming at the problems in designing DSP using HDL，a method of designing DSP based on FPGA which using DSP Builder as Designed tool is pointed out.A 12-order low-pass FIR digital filter was Designed according to the process of Matlab/Simulink/DSP Builder/QuartusⅡ, and the design was verified by the timing simulation based on QuartusⅡand practical test based on SignalTapⅡ. The result shows the Designed filter is correct in function and good in performance.
標(biāo)簽： Builder FPGA DSP 數(shù)字信號處理器
上傳時(shí)間： 2013-11-17
上傳用戶：lo25643
在綜合分析諧波勵(lì)磁無刷同步發(fā)電機(jī)勵(lì)磁控制系統(tǒng)的基礎(chǔ)上,對其勵(lì)磁控制策略進(jìn)行了研究,開發(fā)了一套基于DSP( TMS320F2812) 控制的新型柴油發(fā)電機(jī)勵(lì)磁控制系統(tǒng),該系統(tǒng)采用參數(shù)自適應(yīng)模糊PID 控制勵(lì)磁,選用交流采樣方式實(shí)時(shí)檢測各信號的瞬時(shí)特性,系統(tǒng)仿真結(jié)果以及在1 臺(tái)25 kW 工頻柴油發(fā)電機(jī)上的試驗(yàn)結(jié)果證明了該控制器具有較好的電壓調(diào)節(jié)特性,系統(tǒng)穩(wěn)態(tài)和暫態(tài)性能完全滿足發(fā)電機(jī)對勵(lì)磁系統(tǒng)的要求。關(guān)鍵詞:勵(lì)磁調(diào)節(jié);模糊PID 控制;數(shù)字信號處理器;交流采樣 Abstract :According to the general analysis of the excitation cont rol system of the harmonious wave excitation brushless synchronous generator and it s characteristics ,a new type of diesel generator excitation cont rol system based on DSP( TMS320F2812) was Designed. An adaptive fuzzy PID cont rol of excitation is used in this system. To detect the t ransient characteristics of the signals in a timely manner ,AC sampling was applied.The system simulation result s and the testing result s f rom a 25 kW diesel generator (50 Hz) can prove that the voltage regulation characteristics of the excitation cont rol system are very well ,and both the steadyOstate performance and the t ransient performance of the generator are also good.Key words :excitation cont rol ;fuzzy PID cont rol ;digital signal processor (DSP) ;AC sampling
標(biāo)簽： DSP 柴油發(fā)電機(jī) 勵(lì)磁控制 系統(tǒng)研究
上傳時(shí)間： 2013-10-29
上傳用戶：fxf126@126.com
設(shè)計(jì)一種應(yīng)用于某全地形ATV車載武器裝置中的中控系統(tǒng)，該系統(tǒng)設(shè)計(jì)是以TMS320F2812型DSP為核心，采用模塊化設(shè)計(jì)思想，對其硬件部分進(jìn)行系統(tǒng)設(shè)計(jì)，能夠完成對武器裝置高低、回轉(zhuǎn)方向的運(yùn)動(dòng)控制，實(shí)現(xiàn)靜止或行進(jìn)狀態(tài)中對目標(biāo)物的測距，自動(dòng)瞄準(zhǔn)以及按既定發(fā)射模式發(fā)射彈丸和各項(xiàng)安全性能檢測等功能。通過編制相應(yīng)的軟件，對其進(jìn)行系統(tǒng)調(diào)試，驗(yàn)證了該設(shè)計(jì)運(yùn)行穩(wěn)定。 Abstract: A central control system applied to an ATV vehicle weapons is Designed. The system design is based on TMS320F2812 DSP as the core， uses modular design for its hardware parts. The central control system can complete the motion control of the level of weapons and equipment， rotation direction， to achieve a state of static or moving objects on the target ranging， auto-targeting and according to the established target and the projectile and the launch of the security performance testing and other functions. Through the development of appropriate software and to carry out system testing to verify the stability of this design and operation.
標(biāo)簽： ATV-ATT DSP 中控系統(tǒng)
上傳時(shí)間： 2013-11-02
上傳用戶：jshailingzzh
針對傳統(tǒng)集成電路（ASIC）功能固定、升級困難等缺點(diǎn)，利用FPGA實(shí)現(xiàn)了擴(kuò)頻通信芯片STEL-2000A的核心功能。使用ISE提供的DDS IP核實(shí)現(xiàn)NCO模塊，在下變頻模塊調(diào)用了硬核乘法器并引入CIC濾波器進(jìn)行低通濾波，給出了DQPSK解調(diào)的原理和實(shí)現(xiàn)方法，推導(dǎo)出一種簡便的引入?仔/4固定相移的實(shí)現(xiàn)方法。采用模塊化的設(shè)計(jì)方法使用VHDL語言編寫出源程序，在Virtex-II Pro 開發(fā)板上成功實(shí)現(xiàn)了整個(gè)系統(tǒng)。測試結(jié)果表明該系統(tǒng)正確實(shí)現(xiàn)了STEL-2000A的核心功能。 Abstract: To overcome drawbacks of ASIC such as fixed functionality and upgrade difficulty, FPGA was used to realize the core functions of STEL-2000A. This paper used the DDS IP core provided by ISE to realize the NCO module, called hard core multiplier and implemented CIC filter in the down converter, described the principle and implementation detail of the demodulation of DQPSK, and derived a simple method to introduce a fixed phase shift of ?仔/4. The VHDL source code was Designed by modularity method , and the complete system was successfully implemented on Virtex-II Pro development board. Test results indicate that this system successfully realize the core function of the STEL-2000A.
標(biāo)簽： STEL 2000 FPGA 擴(kuò)頻通信
上傳時(shí)間： 2013-11-06
上傳用戶：liu123
為了在CDMA系統(tǒng)中更好地應(yīng)用QDPSK數(shù)字調(diào)制方式，在分析四相相對移相（QDPSK)信號調(diào)制解調(diào)原理的基礎(chǔ)上，設(shè)計(jì)了一種QDPSK調(diào)制解調(diào)電路，它包括串并轉(zhuǎn)換、差分編碼、四相載波產(chǎn)生和選相、相干解調(diào)、差分譯碼和并串轉(zhuǎn)換電路。在MAX+PLUSⅡ軟件平臺(tái)上，進(jìn)行了編譯和波形仿真。綜合后下載到復(fù)雜可編程邏輯器件EPM7128SLC84-15中，測試結(jié)果表明，調(diào)制電路能正確選相，解調(diào)電路輸出數(shù)據(jù)與QDPSK調(diào)制輸入數(shù)據(jù)完全一致，達(dá)到了預(yù)期的設(shè)計(jì)要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was Designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
標(biāo)簽： QDPSK CPLD 調(diào)制解調(diào) 電路設(shè)計(jì)
上傳時(shí)間： 2014-01-13
上傳用戶：qoovoop
a8259 可編程中斷控制 altera提供 The a8259 is Designed to simplify the implementation of the interrupt interface in 8088 and 8086 based microcomputer systems. The device is known as a programmable interrupt controller. The a8259 receives and prioritizes up to 8 interrupts, and in the cascade mode, this can be expanded up to 64 interrupts. An asynchronous reset and a clock input have been added to improve operation and reliability.
上傳時(shí)間： 2014-11-29
上傳用戶：zhyiroy
針對飛行模擬器座艙數(shù)據(jù)采集的復(fù)雜性，設(shè)計(jì)了一種基于以太網(wǎng)分布式的數(shù)據(jù)采集控制系統(tǒng)，該系統(tǒng)是RCM5700微處理器模塊上的以太網(wǎng)應(yīng)用。在系統(tǒng)的基礎(chǔ)上具體討論了PoE技術(shù)的應(yīng)用，在傳輸數(shù)據(jù)的網(wǎng)線上同時(shí)提供電流，提出并實(shí)現(xiàn)了一種包括輔助電源在內(nèi)的完整可靠的PoE供電方案。設(shè)計(jì)采用美國國家半導(dǎo)體的LM5073和LM5576并根據(jù)不同的負(fù)載情況，進(jìn)行穩(wěn)定可靠的電壓轉(zhuǎn)換，以滿足數(shù)據(jù)采集電路的要求。實(shí)驗(yàn)結(jié)果表明：該設(shè)計(jì)穩(wěn)定可靠，滿足低于13 W的采集節(jié)點(diǎn)供電要求，提高了模擬器信號采集系統(tǒng)的通用性和標(biāo)準(zhǔn)化程度，避免了以往數(shù)據(jù)采集節(jié)點(diǎn)單獨(dú)繁瑣的電源設(shè)計(jì)。 Abstract: Aiming at the complexity of large avion simulation and controlling，the simulator cabin distribute data collecting and control system was Designed. This system is the application of RCM5700 on Ethernet. Based on this system，PoE technique that makes Ethernet can also provide power were expounded with emphasis and included FAUX design the PoE resolution was realized. To achieve the requirement of this system，LM5073 and LM5576 were used to DC-DC switch. From the data of experiment，the design filled the requirement of power-need of node whose power was lower than 13W. The application of the technique can advance the degree of simulation data collections currency and standardization and avoid designing additional power system.
標(biāo)簽： 以太網(wǎng) 分布式 數(shù)據(jù)采集 控制系統(tǒng)
上傳時(shí)間： 2013-11-09
上傳用戶：xyipie
A Computer-On-Module, or COM, is a Module with all components necessary for a bootable host computer, packaged as a super component. A COM requires a Carrier Board to bring out I/O and to power up. COMs are used to build single board computer solutions and offer OEMs fast time-to-market with reduced development cost. Like integrated circuits, they provide OEMs with significant freedom in meeting form-fit-function requirements. For all these reasons the COM methodology has gained much popularity with OEMs in the embedded industry. COM Express® is an open industry standard for Computer-On-Modules. It is Designed to be future proof and to provide a smooth transition path from legacy parallel interfaces to LVDS (Low Voltage Differential Signaling) interfaces. These include the PCI bus and parallel ATA on the one hand and PCI Express and Serial ATA on the other hand.
上傳時(shí)間： 2013-11-05
上傳用戶：Wwill
The CC1101 is a low-cost sub- 1 GHztransceiver Designed for very low-powerwireless applications. The circuit is mainlyintended for the ISM (Industrial, Scientific andMedical) and SRD (Short Range Device)frequency bands at 315, 433, 868, and 915MHz, but can easily be programmed foroperation at other frequencies in the 300-348MHz, 387-464 MHz and 779-928 MHz bands.CC1101 is an improved and code compatibleversion of the CC1100 RF transceiver. Themain improvements on the CC1101 include:
標(biāo)簽： 1110 CC 片上系統(tǒng) 方案
上傳時(shí)間： 2013-11-12
上傳用戶：363186
6小時(shí)學(xué)會(huì)labview, labview Six Hour Course – Instructor Notes This zip file contains material Designed to give students a working knowledge of labview in a 6 hour timeframe. The contents are: Instructor Notes.doc – this document. labviewIntroduction-SixHour.ppt – a PowerPoint presentation containing screenshots and notes on the topics covered by the course. Convert C to F (Ex1).vi – Exercise 1 solution VI. Convert C to F (Ex2).vi – Exercise 2 solution subVI. Thermometer-DAQ (Ex2).vi – Exercise 2 solution VI. Temperature Monitor (Ex3).vi – Exercise 3 solution VI. Thermometer (Ex4).vi – Exercise 4 solution subVI. Convert C to F (Ex4).vi – Exercise 4 solution subVI. Temperature Logger (Ex4).vi – Exercise 4 solution VI. Multiplot Graph (Ex5).vi – Exercise 5 solution VI. Square Root (Ex6).vi – Exercise 6 solution VI. State Machine 1 (Ex7).vi – Exercise 7 solution VI. The slides can be presented in two three hour labs, or six one hour lectures. Depending on the time and resources available in class, you can choose whether to assign the exercises as homework or to be done in class. If you decide to assign the exercises in class, it is best to assign them in order with the presentation. This way the students can create VI’s while the relevant information is still fresh. The notes associated with the exercise slide should be sufficient to guide the students to a solution. The solution files included are one possible solution, but by no means the only solution.
標(biāo)簽： labview
上傳時(shí)間： 2013-10-13
上傳用戶：zjwangyichao
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