虛擬串口軟件
標簽： Virtual Serial Driver Port
上傳時間： 2013-10-27
上傳用戶：1234321@q
MAXQUSBJTAGOW評估板軟件:關鍵特性 Easily Load and Debug Code Interface Provides In-Application Debugging Features Step-by-Step Execution Tracing Breakpointing by Code Address, Data Memory Address, or Register Access Data Memory View and Edit Supports Logic Levels from 1.1V to 3.6V Supports JTAG and 1-Wire Protocols Each Adapter Has Its Own Unique Serial ID, Allowing Multiple Adapters to be Connected Without COM Port Conflicts Has In-Field Upgradable Capability if Firmware Needs to be Upgraded Enclosure Protects from Shorts and ESD
標簽： MAXQUSBJTAGOW 評估板 軟件
上傳時間： 2013-11-23
上傳用戶：truth12
虛擬串口軟件
標簽： Virtual Serial Driver Port
上傳時間： 2013-10-23
上傳用戶：JIUSHICHEN
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-21
上傳用戶：wxqman
3 FPGA設計流程 完整的FPGA 設計流程包括邏輯電路設計輸入、功能仿真、綜合及時序分析、實現、加載配置、調試。FPGA 配置就是將特定的應用程序設計按FPGA設計流程轉化為數據位流加載到FPGA 的內部存儲器中，實現特定邏輯功能的過程。由于FPGA 電路的內部存儲器都是基于RAM 工藝的，所以當FPGA電路電源掉電后，內部存儲器中已加載的位流數據將隨之丟失。所以，通常將設計完成的FPGA 位流數據存于外部存儲器中，每次上電自動進行FPGA電路配置加載。 4 FPGA配置原理 以Xilinx公司的Qpro Virtex Hi-Rel系列XQV100電路為例，FPGA的配置模式有四種方案可選擇：MasterSerial Mode，Slave Serial Mode，Master selectMAPMode，Slave selectMAP Mode。配置是通過芯片上的一組專/ 復用引腳信號完成的，主要配置功能信號如下： (1)M0、M1、M2：下載配置模式選擇; (2)CLK：配置時鐘信號; (3)DONE：顯示配置狀態、控制器件啟動;
上傳時間： 2013-11-18
上傳用戶：oojj
This application note provides users with a general understanding of the SVF and XSVF fileformats as they apply to Xilinx devices. Some familiarity with IEEE STD 1149.1 (JTAG) isassumed. For information on using Serial Vector Format (SVF) and Xilinx Serial Vector Format(XSVF) files in embedded programming applications
上傳時間： 2015-01-02
上傳用戶：時代將軍
This application note shows how to achieve low-cost, efficient serial configuration for Spartan FPGA designs. The approachrecommended here takes advantage of unused resources in a design, thereby reducing the cost, part count, memory size,and board space associated with the serial configuration circuitry. As a result, neither processor nor PROM needs to be fullydedicated to performing Spartan configuration.In particular, information is provided on how the idle processing time of an on-board controller can be used to loadconfiguration data from an off-board source. As a result, it is possible to upgrade a Spartan design in the field by sending thebitstream over a network.
上傳時間： 2013-11-01
上傳用戶：wojiaohs
為了在CDMA系統中更好地應用QDPSK數字調制方式，在分析四相相對移相（QDPSK)信號調制解調原理的基礎上，設計了一種QDPSK調制解調電路，它包括串并轉換、差分編碼、四相載波產生和選相、相干解調、差分譯碼和并串轉換電路。在MAX+PLUSⅡ軟件平臺上，進行了編譯和波形仿真。綜合后下載到復雜可編程邏輯器件EPM7128SLC84-15中，測試結果表明，調制電路能正確選相，解調電路輸出數據與QDPSK調制輸入數據完全一致，達到了預期的設計要求。 Abstract: In order to realize the better application of digital modulation mode QDPSK in the CDMA system， a sort of QDPSK modulation-demodulation circuit was designed based on the analysis of QDPSK signal modulation-demodulation principles. It included serial/parallel conversion circuit, differential encoding circuit, four-phase carrier wave produced and phase chosen circuit, coherent demodulation circuit, difference decoding circuit and parallel/serial conversion circuit. And it was compiled and simulated on the MAX+PLUSⅡ software platform,and downloaded into the CPLD of EPM7128SLC84-15.The test result shows that the modulation circuit can exactly choose the phase，and the output data of the demodulator circuit is the same as the input data of the QDPSK modulate. The circuit achieves the prospective requirement of the design.
上傳時間： 2013-10-28
上傳用戶：jyycc
The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper includes example design, testbench; and both implementation and simulation scripts
標簽： Transceiver Virtex Wizar GTP
上傳時間： 2013-10-20
上傳用戶：dave520l
這個軟件需要你的本機操作的。其他機器是算不出來的！ 就是說 一臺電腦只有一個注冊碼對應！ 這里有個辦法： MULTISIM2001安裝方法： 一：運行SETUP.EXE安裝。在安裝時，要重新啟動計算機一次。 二：啟動后在“開始>程序”中找到STARTUP項，運行后，繼續進行安裝，安裝過程中，第一次要求輸入“CODE"碼時， 輸入“PP-0411-48015-7464-32084"輸入后，會提示"VALID SERIAL NUMBER FOR MULTISIM 2001 POWER-PRO." 按確定，又會出現一個“feature code”框，輸入“FC-6424-04180-0044-13881”后， 在彈出的對話框中選擇“取消”，一路確定即可完成安裝。 三：1.運行VERILOG目錄內的SETUP安裝 2.運行FPGA目錄內的SETUP安裝 3.將CRACK目錄內的LICMGR.DLL拷貝到WINDOWS系統的SYSTEM 目錄內 4.并將VERILOG安裝目錄內的同名文件刪除 5.將SILOS.LIC文件拷到VERILOG安裝目錄內覆蓋原文件，并作如下編輯： 6.將“COMPUTER_NAME”替換為你的機器名 7.將“D:\MULTISIM\VERILOG\PATH_TO_SIMUCAD.EXE”替換為你的 實際安裝路徑。如此你便可以使用VERILOG了。 四：安裝之后，運行MULTISIM2001,會要求輸入“RELEASE CODE",不用著急， 記下“SERIAL NUMBER"和“SIGNATURE NUMBER", 使用CRACK目錄內的注冊器“MULTISIM KEYGEN.EXE" 將剛才記下的兩個號碼分別填入后， 即可得到"RELEASE CODE", 以后就可以正常使用了。 五：接下來運行 database update目錄中的幾個文件， 進行數據庫合并即可。祝你成功！！ 六：啟動MULTISIM2001時候的注冊碼 1： PP-0411-48015-7464-32084 2： 37506-86380 3:的三個空格 1975 2711 4842 里面包含了：Multisim2001漢化破解版、Multisim.V10.0.1.漢化破解版圖解 解壓密碼：www.pp51.com
上傳時間： 2013-11-16
上傳用戶：天空說我在
