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Fire-Workflow-<b>engine</b>-All-In-One

  • In computer vision, sets of data acquired by sampling the same scene or object at different times, o

    In computer vision, sets of data acquired by sampling the same scene or object at different times, or from different perspectives, will be in different coordinate systems. Image registration is the process of transforming the different sets of data into one coordinate system. Registration is necessary in order to be able to compare or integrate the data obtained from different measurements. Image registration is the process of transforming the different sets of data into one coordinate system. To be precise it involves finding transformations that relate spatial information conveyed in one image to that in another or in physical space. Image registration is performed on a series of at least two images, where one of these images is the reference image to which all the others will be registered. The other images are referred to as target images.

    標(biāo)簽: different computer acquired sampling

    上傳時(shí)間: 2013-12-28

    上傳用戶:來茴

  • Antennas: For All Applications(2nd Edition) by John D. Kraus

    ·JOHN DANIEL KRAUS: 94 DIED 18 July 2004 MEMBER GRADE Life Fellow EDUCATION Bachelors, masters, and doctorate-all in physics from the University of Michigan, Ann Arbor, USA FIELDS OF INTEREST Electroma

    標(biāo)簽: nbsp Applications Antennas Edition

    上傳時(shí)間: 2013-07-29

    上傳用戶:ukuk

  • 電源工程師-電路設(shè)計(jì)中的英雄

    Abstract: We don't expect manufacturers to produce clothes that in one size that fits everyone. In thesame way, one ESD component can't solve all issues—each application has different ESD requirements.Knowing that "one size fits all" cannot apply to power design, the power designer, or the engineering"super hero," must consider all the potential disruptions to a steady flow of power and thenvarious waysto mitigate them. This tutorial describes voltage- and current-limiting devices and risetime reducers tomanage the power. It also points to free and low-cost software tools to help design lowpass filters, checkcapacitor self-resonance, and simulate circuits.

    標(biāo)簽: 電源工程師 電路設(shè)計(jì)

    上傳時(shí)間: 2013-11-18

    上傳用戶:zhouxuepeng1

  • PL2303 USB to Serial Adapter

    The PL2303 USB to Serial adapter is your smart and convenient accessory forconnecting RS-232 serial devices to your USB-equipped Windows host computer. Itprovides a bridge connection with a standard DB 9-pin male serial port connector inone end and a standard Type-A USB plug connector on the other end. You simplyattach the serial device onto the serial port of the cable and plug the USB connectorinto your PC USB port. It allows a simple and easy way of adding serial connectionsto your PC without having to go thru inserting a serial card and traditional portconfiguration.This USB to Serial adapter is ideal for connecting modems, cellular phones, PDAs,digital cameras, card readers and other serial devices to your computer. It providesserial connections up to 1Mbps of data transfer rate. And since USB does not requireany IRQ resource, more devices can be attached to the system without the previoushassles of device and resource conflicts.Finally, the PL-2303 USB to Serial adapter is a fully USB Specification compliantdevice and therefore supports advanced power management such as suspend andresume operations as well as remote wakeup. The PL-2303 USB Serial cable adapteris designed to work on all Windows operating systems.

    標(biāo)簽: Adapter Serial 2303 USB

    上傳時(shí)間: 2013-11-01

    上傳用戶:ghostparker

  • 數(shù)字運(yùn)算

    數(shù)字運(yùn)算,判斷一個(gè)數(shù)是否接近素?cái)?shù) A Niven number is a number such that the sum of its digits divides itself. For example, 111 is a Niven number because the sum of its digits is 3, which divides 111. We can also specify a number in another base b, and a number in base b is a Niven number if the sum of its digits divides its value. Given b (2 <= b <= 10) and a number in base b, determine whether it is a Niven number or not. Input Each line of input contains the base b, followed by a string of digits representing a positive integer in that base. There are no leading zeroes. The input is terminated by a line consisting of 0 alone. Output For each case, print "yes" on a line if the given number is a Niven number, and "no" otherwise. Sample Input 10 111 2 110 10 123 6 1000 8 2314 0 Sample Output yes yes no yes no

    標(biāo)簽: 數(shù)字 運(yùn)算

    上傳時(shí)間: 2015-05-21

    上傳用戶:daguda

  • The government of a small but important country has decided that the alphabet needs to be streamline

    The government of a small but important country has decided that the alphabet needs to be streamlined and reordered. Uppercase letters will be eliminated. They will issue a royal decree in the form of a String of B and A characters. The first character in the decree specifies whether a must come ( B )Before b in the new alphabet or ( A )After b . The second character determines the relative placement of b and c , etc. So, for example, "BAA" means that a must come Before b , b must come After c , and c must come After d . Any letters beyond these requirements are to be excluded, so if the decree specifies k comparisons then the new alphabet will contain the first k+1 lowercase letters of the current alphabet. Create a class Alphabet that contains the method choices that takes the decree as input and returns the number of possible new alphabets that conform to the decree. If more than 1,000,000,000 are possible, return -1. Definition

    標(biāo)簽: government streamline important alphabet

    上傳時(shí)間: 2015-06-09

    上傳用戶:weixiao99

  • Swfdec is a decoder/renderer for Macromedia Flash animations. The decoding and rendering engine is

    Swfdec is a decoder/renderer for Macromedia Flash animations. The decoding and rendering engine is provided in a library that can be used by other applications

    標(biāo)簽: Macromedia animations rendering decoding

    上傳時(shí)間: 2016-01-08

    上傳用戶:rocketrevenge

  • We have a group of N items (represented by integers from 1 to N), and we know that there is some tot

    We have a group of N items (represented by integers from 1 to N), and we know that there is some total order defined for these items. You may assume that no two elements will be equal (for all a, b: a<b or b<a). However, it is expensive to compare two items. Your task is to make a number of comparisons, and then output the sorted order. The cost of determining if a < b is given by the bth integer of element a of costs (space delimited), which is the same as the ath integer of element b. Naturally, you will be judged on the total cost of the comparisons you make before outputting the sorted order. If your order is incorrect, you will receive a 0. Otherwise, your score will be opt/cost, where opt is the best cost anyone has achieved and cost is the total cost of the comparisons you make (so your score for a test case will be between 0 and 1). Your score for the problem will simply be the sum of your scores for the individual test cases.

    標(biāo)簽: represented integers group items

    上傳時(shí)間: 2016-01-17

    上傳用戶:jeffery

  • Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH

    Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.

    標(biāo)簽: SHIFTER name module Input

    上傳時(shí)間: 2013-12-13

    上傳用戶:himbly

  • Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGH

    Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.

    標(biāo)簽: SHIFTER name module Input

    上傳時(shí)間: 2014-01-20

    上傳用戶:三人用菜

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