FIFO電路(first in，first out)，內部藏有１６ｂｉｔ×１６ｗｏｒｄ的Dual port RAM，依次讀出已經寫入的數據。因為不存在Address輸入，所以請自行設計內藏的讀寫指針。由FIFO電路輸出的EF信號(表示RAM內部的數據為空)和FF信號(表示RAM內部的數據為滿)來表示RAM內部的狀態，并且控制FIFO的輸入信號WEN(寫使能)和REN(讀使能)。以及為了更好得控制FIFO電路，AEF(表示RAM內部的數據即將空)信號也同時輸出。
Synthesizable FIFO Model
This example describes a synthesizable implementation of a FIFO. The FIFO depth and FIFO width in bits can be modified by simply changing the value of two parameters, `FWIDTH and `FDEPTH. For this example, the FIFO depth is 4 and the FIFO width is 32 bits.
This program is copyrighted by it s author and you are granted a free license
to use the program for non-commercial purposes. If you are interested in
using the program for commercial purposes please contact Kevin W. Russell
at CIS 71551,253 for licensing information.
