微處理器及微型計算機的發(fā)展概況 第一代微處理器是以Intel公司1971年推出的4004,4040為代表的四位微處理機。 第二代微處理機(1973年~1977年),典型代表有:Intel 公司的8080、8085;Motorola公司的M6800以及Zlog公司的Z80。 第三代微處理機 第三代微機是以16位機為代表,基本上是在第二代微機的基礎(chǔ)上發(fā)展起來的。其中Intel公司的8088。8086是在8085的基礎(chǔ)發(fā)展起來的;M68000是Motorola公司在M6800 的基礎(chǔ)發(fā)展起來的; 第四代微處理機 以Intel公司1984年10月推出的80386CPU和1989年4月推出的80486CPU為代表, 第五代微處理機的發(fā)展更加迅猛,1993年3月被命名為PENTIUM的微處理機面世,98年P(guān)ENTIUM 2又被推向市場。 INTEL CPU 發(fā)展歷史Intel第一塊CPU 4004,4位主理器,主頻108kHz,運算速度0.06MIPs(Million Instructions Per Second, 每秒百萬條指令),集成晶體管2,300個,10微米制造工藝,最大尋址內(nèi)存640 bytes,生產(chǎn)曰期1971年11月. 8085,8位主理器,主頻5M,運算速度0.37MIPs,集成晶體管6,500個,3微米制造工藝,最大尋址內(nèi)存64KB,生產(chǎn)曰期1976年 8086,16位主理器,主頻4.77/8/10MHZ,運算速度0.75MIPs,集成晶體管29,000個,3微米制造工藝,最大尋址內(nèi)存1MB,生產(chǎn)曰期1978年6月. 80486DX,DX2,DX4,32位主理器,主頻25/33/50/66/75/100MHZ,總線頻率33/50/66MHZ,運算速度20~60MIPs,集成晶體管1.2M個,1微米制造工藝,168針PGA,最大尋址內(nèi)存4GB,緩存8/16/32/64KB,生產(chǎn)曰期1989年4月 Celeron一代, 主頻266/300MHZ(266/300MHz w/o L2 cache, Covington芯心 (Klamath based),300A/333/366/400/433/466/500/533MHz w/128kB L2 cache, Mendocino核心 (Deschutes-based), 總線頻率66MHz,0.25微米制造工藝,生產(chǎn)曰期1998年4月) Pentium 4 (478針),至今分為三種核心:Willamette核心(主頻1.5G起,FSB400MHZ,0.18微米制造工藝),Northwood核心(主頻1.6G~3.0G,FSB533MHZ,0.13微米制造工藝, 二級緩存512K),Prescott核心(主頻2.8G起,FSB800MHZ,0.09微米制造工藝,1M二級緩存,13條全新指令集SSE3),生產(chǎn)曰期2001年7月. 更大的緩存、更高的頻率、 超級流水線、分支預測、亂序執(zhí)行超線程技術(shù) 微型計算機組成結(jié)構(gòu)單片機簡介單片機即單片機微型計算機,是將計算機主機(CPU、 內(nèi)存和I/O接口)集成在一小塊硅片上的微型機。 三、計算機編程語言的發(fā)展概況 機器語言 機器語言就是0,1碼語言,是計算機唯一能理解并直接執(zhí)行的語言。匯編語言 用一些助記符號代替用0,1碼描述的某種機器的指令系統(tǒng),匯編語言就是在此基礎(chǔ)上完善起來的。高級語言 BASIC,PASCAL,C語言等等。用高級語言編寫的程序稱源程序,它們必須通過編譯或解釋,連接等步驟才能被計算機處理。 面向?qū)ο笳Z言 C++,Java等編程語言是面向?qū)ο蟮恼Z言。 1.3 微型計算機中信息的表示及運算基礎(chǔ)(一) 十進制ND有十個數(shù)碼:0~9,逢十進一。 例 1234.5=1×103 +2×102 +3×101 +4×100 +5×10-1加權(quán)展開式以10稱為基數(shù),各位系數(shù)為0~9,10i為權(quán)。 一般表達式:ND= dn-1×10n-1+dn-2×10n-2 +…+d0×100 +d-1×10-1+… (二) 二進制NB兩個數(shù)碼:0、1, 逢二進一。 例 1101.101=1×23+1×22+0×21+1×20+1×2-1+1×2-3 加權(quán)展開式以2為基數(shù),各位系數(shù)為0、1, 2i為權(quán)。 一般表達式: NB = bn-1×2n-1 + bn-2×2n-2 +…+b0×20 +b-1×2-1+… (三)十六進制NH十六個數(shù)碼0~9、A~F,逢十六進一。 例:DFC.8=13×162 +15×161 +12×160 +8×16-1 展開式以十六為基數(shù),各位系數(shù)為0~9,A~F,16i為權(quán)。 一般表達式: NH= hn-1×16n-1+ hn-2×16n-2+…+ h0×160+ h-1×16-1+… 二、不同進位計數(shù)制之間的轉(zhuǎn)換 (二)二進制與十六進制數(shù)之間的轉(zhuǎn)換 24=16 ,四位二進制數(shù)對應一位十六進制數(shù)。舉例:(三)十進制數(shù)轉(zhuǎn)換成二、十六進制數(shù)整數(shù)、小數(shù)分別轉(zhuǎn)換 1.整數(shù)轉(zhuǎn)換法“除基取余”:十進制整數(shù)不斷除以轉(zhuǎn)換進制基數(shù),直至商為0。每除一次取一個余數(shù),從低位排向高位。舉例: 2. 小數(shù)轉(zhuǎn)換法“乘基取整”:用轉(zhuǎn)換進制的基數(shù)乘以小數(shù)部分,直至小數(shù)為0或達到轉(zhuǎn)換精度要求的位數(shù)。每乘一次取一次整數(shù),從最高位排到最低位。舉例: 三、帶符號數(shù)的表示方法 機器數(shù):機器中數(shù)的表示形式。真值: 機器數(shù)所代表的實際數(shù)值。舉例:一個8位機器數(shù)與它的真值對應關(guān)系如下: 真值: X1=+84=+1010100B X2=-84= -1010100B 機器數(shù):[X1]機= 01010100 [X2]機= 11010100(二)原碼、反碼、補碼最高位為符號位,0表示 “+”,1表示“-”。 數(shù)值位與真值數(shù)值位相同。 例 8位原碼機器數(shù): 真值: x1 = +1010100B x2 =- 1010100B 機器數(shù): [x1]原 = 01010100 [x2]原 = 11010100原碼表示簡單直觀,但0的表示不唯一,加減運算復雜。 正數(shù)的反碼與原碼表示相同。 負數(shù)反碼符號位為 1,數(shù)值位為原碼數(shù)值各位取反。 例 8位反碼機器數(shù): x= +4: [x]原= 00000100 [x]反= 00000100 x= -4: [x]原= 10000100 [x]反= 111110113、補碼(Two’s Complement)正數(shù)的補碼表示與原碼相同。 負數(shù)補碼等于2n-abs(x)8位機器數(shù)表示的真值四、 二進制編碼例:求十進制數(shù)876的BCD碼 876= 1000 0111 0110 BCD 876= 36CH = 1101101100B 2、字符編碼 美國標準信息交換碼ASCII碼,用于計算 機與計算機、計算機與外設(shè)之間傳遞信息。 3、漢字編碼 “國家標準信息交換用漢字編碼”(GB2312-80標準),簡稱國標碼。 用兩個七位二進制數(shù)編碼表示一個漢字 例如“巧”字的代碼是39H、41H漢字內(nèi)碼例如“巧”字的代碼是0B9H、0C1H1·4 運算基礎(chǔ) 一、二進制數(shù)的運算加法規(guī)則:“逢2進1” 減法規(guī)則:“借1當2” 乘法規(guī)則:“逢0出0,全1出1”二、二—十進制數(shù)的加、減運算 BCD數(shù)的運算規(guī)則 循十進制數(shù)的運算規(guī)則“逢10進1”。但計算機在進行這種運算時會出現(xiàn)潛在的錯誤。為了解決BCD數(shù)的運算問題,采取調(diào)整運算結(jié)果的措施:即“加六修正”和“減六修正”例:10001000(BCD)+01101001(BCD) =000101010111(BCD) 1 0 0 0 1 0 0 0 + 0 1 1 0 1 0 0 1 1 1 1 1 0 0 0 1 + 0 1 1 0 0 1 1 0 ……調(diào)整 1 0 1 0 1 0 1 1 1 進位 例: 10001000(BCD)- 01101001(BCD)= 00011001(BCD) 1 0 0 0 1 0 0 0 - 0 1 1 0 1 0 0 1 0 0 0 1 1 1 1 1 - 0 1 1 0 ……調(diào)整 0 0 0 1 1 0 0 1 三、 帶符號二進制數(shù)的運算 1.5 幾個重要的數(shù)字邏輯電路編碼器譯碼器計數(shù)器微機自動工作的條件程序指令順序存放自動跟蹤指令執(zhí)行1.6 微機基本結(jié)構(gòu)微機結(jié)構(gòu)各部分組成連接方式1、以CPU為中心的雙總線結(jié)構(gòu);2、以內(nèi)存為中心的雙總線結(jié)構(gòu);3、單總線結(jié)構(gòu)CPU結(jié)構(gòu)管腳特點 1、多功能;2、分時復用內(nèi)部結(jié)構(gòu) 1、控制; 2、運算; 3、寄存器; 4、地址程序計數(shù)器堆棧定義 1、定義;2、管理;3、堆棧形式
上傳時間: 2013-10-17
上傳用戶:erkuizhang
針對使用硬件描述語言進行設(shè)計存在的問題,提出一種基于FPGA并采用DSP Builder作為設(shè)計工具的數(shù)字信號處理器設(shè)計方法。并按照Matlab/Simulink/DSP Builder/QuartusⅡ設(shè)計流程,設(shè)計了一個12階FIR 低通數(shù)字濾波器,通過Quartus 時序仿真及嵌入式邏輯分析儀SignalTapⅡ硬件測試對設(shè)計進行了驗證。結(jié)果表明,所設(shè)計的FIR 濾波器功能正確,性能良好。 Abstract: Aiming at the problems in designing DSP using HDL,a method of designing DSP based on FPGA which using DSP Builder as designed tool is pointed out.A 12-order low-pass FIR digital filter was designed according to the process of Matlab/Simulink/DSP Builder/QuartusⅡ, and the design was verified by the timing simulation based on QuartusⅡand practical test based on SignalTapⅡ. The result shows the designed filter is correct in function and good in performance.
標簽: Builder FPGA DSP 數(shù)字信號處理器
上傳時間: 2013-11-17
上傳用戶:lo25643
在綜合分析諧波勵磁無刷同步發(fā)電機勵磁控制系統(tǒng)的基礎(chǔ)上,對其勵磁控制策略進行了研究,開發(fā)了一套基于DSP( TMS320F2812) 控制的新型柴油發(fā)電機勵磁控制系統(tǒng),該系統(tǒng)采用參數(shù)自適應模糊PID 控制勵磁,選用交流采樣方式實時檢測各信號的瞬時特性,系統(tǒng)仿真結(jié)果以及在1 臺25 kW 工頻柴油發(fā)電機上的試驗結(jié)果證明了該控制器具有較好的電壓調(diào)節(jié)特性,系統(tǒng)穩(wěn)態(tài)和暫態(tài)性能完全滿足發(fā)電機對勵磁系統(tǒng)的要求。關(guān)鍵詞:勵磁調(diào)節(jié);模糊PID 控制;數(shù)字信號處理器;交流采樣 Abstract :According to the general analysis of the excitation cont rol system of the harmonious wave excitation brushless synchronous generator and it s characteristics ,a new type of diesel generator excitation cont rol system based on DSP( TMS320F2812) was designed. An adaptive fuzzy PID cont rol of excitation is used in this system. To detect the t ransient characteristics of the signals in a timely manner ,AC sampling was applied.The system simulation result s and the testing result s f rom a 25 kW diesel generator (50 Hz) can prove that the voltage regulation characteristics of the excitation cont rol system are very well ,and both the steadyOstate performance and the t ransient performance of the generator are also good.Key words :excitation cont rol ;fuzzy PID cont rol ;digital signal processor (DSP) ;AC sampling
標簽: DSP 柴油發(fā)電機 勵磁控制 系統(tǒng)研究
上傳時間: 2013-10-29
上傳用戶:fxf126@126.com
設(shè)計一種應用于某全地形ATV車載武器裝置中的中控系統(tǒng),該系統(tǒng)設(shè)計是以TMS320F2812型DSP為核心,采用模塊化設(shè)計思想,對其硬件部分進行系統(tǒng)設(shè)計,能夠完成對武器裝置高低、回轉(zhuǎn)方向的運動控制,實現(xiàn)靜止或行進狀態(tài)中對目標物的測距,自動瞄準以及按既定發(fā)射模式發(fā)射彈丸和各項安全性能檢測等功能。通過編制相應的軟件,對其進行系統(tǒng)調(diào)試,驗證了該設(shè)計運行穩(wěn)定。 Abstract: A central control system applied to an ATV vehicle weapons is designed. The system design is based on TMS320F2812 DSP as the core, uses modular design for its hardware parts. The central control system can complete the motion control of the level of weapons and equipment, rotation direction, to achieve a state of static or moving objects on the target ranging, auto-targeting and according to the established target and the projectile and the launch of the security performance testing and other functions. Through the development of appropriate software and to carry out system testing to verify the stability of this design and operation.
標簽: ATV-ATT DSP 中控系統(tǒng)
上傳時間: 2013-11-02
上傳用戶:jshailingzzh
針對運行中火車測速運用多普勒效應采用DSP 設(shè)計雷達測速系統(tǒng)并闡述了其基本設(shè)計思想與工作原理給出系統(tǒng)硬件軟件設(shè)計結(jié)構(gòu)和原理圖改善了原有光電測速精度提高了系統(tǒng)工作穩(wěn)定性和可靠性經(jīng)實驗證明DSP 采集板工作穩(wěn)定測速效果好關(guān)鍵詞DSP; 雷達測速; 多普勒效應 On Board DSP-Based Radar Speed Measurement System TANG Wei, SUN Zhi-fang, CHEN Quan (Dept.of computer Science,Yangtze University,Jingzhou 434023,China)Abstract: This paper presents a DSP-based train speed measurement by using Doppler radar. The structure of the system is introduced.The hardware and software are also discussed.Key words: DSP; rader speed measurement; doppler principle
標簽: DSP 車載 系統(tǒng)設(shè)計 雷達測速
上傳時間: 2013-10-27
上傳用戶:003030
This white paper discusses how market trends, the need for increased productivity, and new legislation have accelerated the use of safety systems in industrial machinery. This TÜV-qualified FPGA design methodology is changing the paradigms of safety designs and will greatly reduce development effort, system complexity, and time to market. This allows FPGA users to design their own customized safety controllers and provides a significant competitive advantage over traditional microcontroller or ASIC-based designs. Introduction The basic motivation of deploying functional safety systems is to ensure safe operation as well as safe behavior in cases of failure. Examples of functional safety systems include train brakes, proximity sensors for hazardous areas around machines such as fast-moving robots, and distributed control systems in process automation equipment such as those used in petrochemical plants. The International Electrotechnical Commission’s standard, IEC 61508: “Functional safety of electrical/electronic/programmable electronic safety-related systems,” is understood as the standard for designing safety systems for electrical, electronic, and programmable electronic (E/E/PE) equipment. This standard was developed in the mid-1980s and has been revised several times to cover the technical advances in various industries. In addition, derivative standards have been developed for specific markets and applications that prescribe the particular requirements on functional safety systems in these industry applications. Example applications include process automation (IEC 61511), machine automation (IEC 62061), transportation (railway EN 50128), medical (IEC 62304), automotive (ISO 26262), power generation, distribution, and transportation. 圖Figure 1. Local Safety System
標簽: FPGA 安全系統(tǒng)
上傳時間: 2013-11-05
上傳用戶:維子哥哥
Designing withProgrammable Logicin an Analog WorldProgrammable logic devicesrevolutionized digital design over 25years ago, promising designers a blankchip to design literally any functionand program it in the field. PLDs canbe low-logic density devices that usenonvolatile sea-of-gates cells calledcomplex programmable logic devices(CPLDs) or they can be high-densitydevices based on SRAM look-up tables
標簽: Solutions Analog Xilinx FPGAs
上傳時間: 2013-11-01
上傳用戶:a67818601
WP369可擴展式處理平臺-各種嵌入式系統(tǒng)的理想解決方案 :Delivering unrivaled levels of system performance,flexibility, scalability, and integration to developers,Xilinx's architecture for a new Extensible Processing Platform is optimized for system power, cost, and size. Based on ARM's dual-core Cortex™-A9 MPCore processors and Xilinx’s 28 nm programmable logic,the Extensible Processing Platform takes a processor-centric approach by defining a comprehensive processor system implemented with standard design methods. This approach provides Software Developers a familiar programming environment within an optimized, full featured,powerful, yet low-cost, low-power processing platform.
上傳時間: 2013-10-22
上傳用戶:685
The Xilinx Zynq-7000 Extensible Processing Platform (EPP) redefines the possibilities for embedded systems, giving system and software architects and developers a flexible platform to launch their new solutions and traditional ASIC and ASSP users an alternative that aligns with today’s programmable imperative. The new class of product elegantly combines an industrystandard ARMprocessor-based system with Xilinx 28nm programmable logic—in a single device. The processor boots first, prior to configuration of the programmable logic. This, along with a streamlined workflow, saves time and effort and lets software developers and hardware designers start development simultaneously.
上傳時間: 2013-11-01
上傳用戶:dingdingcandy
SRAM-based FPGAs are non-volatile devices. Upon powerup, They are required to be programmed from an external source. This procedure allows anyone to easily monitor the bit-stream, and clone the device. The problem then becomes how can you effectively protect your intellectual property from others in an architecture where the part is externally programmed?
標簽: FPGA PLD 數(shù)據(jù)加密
上傳時間: 2013-11-06
上傳用戶:wl9454
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