-
本文簡單介紹了MCGS 組態(tài)軟件和SPCE061A 單片機(jī)的特點，即北京昆侖通態(tài)自動化軟件科技有限公司的工控組態(tài)軟件MCGS(Monitor and Control Generated System )和臺灣凌陽科技推出的16 位微控制器SPCE061A，重點介紹了如何一步步開發(fā)SPCE061A 單片機(jī)的驅(qū)動程序，并簡單介紹了下位機(jī)程序的設(shè)計，最后給出了測試情況。計算機(jī)技術(shù)的飛速發(fā)展為工業(yè)自動化開辟了廣闊的發(fā)展空間，人們可以快捷地開發(fā)和組建高效的控制系統(tǒng)。筆者設(shè)計的液體點滴監(jiān)控模型,可以對液體點滴情況實現(xiàn)遠(yuǎn)程監(jiān)控和現(xiàn)場監(jiān)控，終端和上位機(jī)均可人工設(shè)定所需的液體點滴速度并動態(tài)顯示。在這方面，MCGS 工控組態(tài)軟件提供了強有力的支持，它是一套Windows 環(huán)境下快速構(gòu)造和生成上位機(jī)監(jiān)控系統(tǒng)的組態(tài)軟件系統(tǒng)，可快速構(gòu)造和生成數(shù)據(jù)采集、報警處理、流程控制、動畫顯示、報表輸出等界面,實現(xiàn)各種工程曲線的繪制、報表輸出、遠(yuǎn)程通信等功能 [1]。MCGS 作為一種方便有效的通用工控軟件,它提供了國內(nèi)外各種常用的工控設(shè)備的驅(qū)動程序。但在實際應(yīng)用中,因為所用設(shè)備的特殊性,允許用戶根據(jù)需要來定制設(shè)備驅(qū)動程序。MCGS 用Active DLL 構(gòu)件實現(xiàn)設(shè)備驅(qū)動程序,通過規(guī)范的OLE 接口掛接到MCGS 中,使其構(gòu)成一個整體。鑒于Visual Basic 語言的通用性和簡單性,使用VB 來開發(fā)單片機(jī)驅(qū)動,MCGS 的實現(xiàn)方法和原理與標(biāo)準(zhǔn)的Active DLL 完全一致,但MCGS 規(guī)定了一套接口規(guī)范,只有遵守這些接口規(guī)范的Active DLL 才能用作MCGS 的設(shè)備驅(qū)動構(gòu)件。利用具有語音和 DSP 功能的SPCE061A 單片機(jī)作為液體點滴監(jiān)控模型的核心控制器，SPCE061A 是臺灣凌陽科技推出的16 位微控制器，提供了豐富的軟、硬件資源，開發(fā)靈活方便。除此之外SPCE061A 的最高時鐘頻率可達(dá)到49MHz,具有運算速度高的優(yōu)勢，這為語音的錄制和播放提供了條件[4]。
標(biāo)簽：
MCGS
凌陽單片機(jī)
驅(qū)動程序
上傳時間：
2013-12-19
上傳用戶：leesuper
-
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are Generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined TTL-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
標(biāo)簽：
Signal
Input
Fall
Rise
上傳時間：
2013-10-23
上傳用戶：copu
-
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between TTL-VIL and TTL-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of theTTL-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for TTL components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are Generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
標(biāo)簽：
C16x
微控制器
輸入信號
時序圖
上傳時間：
2014-04-02
上傳用戶：han_zh
-
The STWD100 watchdog timer circuits are self-contained devices which prevent systemfailures that are caused by certain types of hardware errors (non-responding peripherals,bus contention, etc.) or software errors (bad code jump, code stuck in loop, etc.).The STWD100 watchdog timer has an input, WDI, and an output, WDO (see Figure 2). Theinput is used to clear the internal watchdog timer periodically within the specified timeoutperiod, twd (see Section 3: Watchdog timing). While the system is operating correctly, itperiodically toggles the watchdog input, WDI. If the system fails, the watchdog timer is notreset, a system alert is Generated and the watchdog output, WDO, is asserted (seeSection 3: Watchdog timing).The STWD100 circuit also has an enable pin, EN (see Figure 2), which can enable ordisable the watchdog functionality. The EN pin is connected to the internal pull-downresistor. The device is enabled if the EN pin is left floating.
標(biāo)簽：
3.3
看門狗
芯片
上傳時間：
2013-10-22
上傳用戶：taiyang250072
-
為了擴(kuò)大監(jiān)控范圍，提高資源利用率，降低系統(tǒng)成本，提出了一種多通道視頻切換的解決方案。首先從視頻信號分離出行場信號，然后根據(jù)行場信號由DSP和FPGA產(chǎn)生控制信號，控制多路視頻通道之間的切換，從而實現(xiàn)讓一個視頻處理器同時監(jiān)控不同場景。實驗結(jié)果表明，該方案可以在視頻監(jiān)控告警系統(tǒng)中穩(wěn)定、可靠地實現(xiàn)視頻通道的切換。
Abstract:
To expand the scope of monitoring， improve resource utilization， reduce system cost， a multiple video channels signal switching method is pointed out in this paper. First， horizontal sync signal and field sync signal from the video signal are separated， then control signal according to the sync signal by DSP and FPGA is Generated to control the switching between multiple video channels. Thus， it achieves to make a video processor to monitor different place. Experimental results show that the method can realize video channel switching reliably， and is applied in the video monitoring warning system successfully.
標(biāo)簽：
FPGA
DSP
視頻通道
切換控制
上傳時間：
2013-11-09
上傳用戶：不懂夜的黑
-
Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat Generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
標(biāo)簽：
封裝
器件
用戶
賽靈思
上傳時間：
2013-10-22
上傳用戶：ztj182002
-
This example shows how to update at regulate period the WWDG counter using theEarly Wakeup interrupt (EWI).
The WWDG timeout is set to 262ms, refresh window set to 41h and the EWI isenabled. When the WWDG counter reaches 40h the EWI is Generated and in the WWDGISR the counter is refreshed to prevent a WWDG reset and led connected to PC.07is toggled.The EXTI line9 is connected to PB.09 pin and configured to generate an interrupton falling edge.In the NVIC, EXTI line9 to 5 interrupt vector is enabled with priority equal to 0and the WWDG interrupt vector is enabled with priority equal to 1 (EXTI IT > WWDG IT).
The EXTI Line9 will be used to simulate a software failure: once the EXTI line9event occurs (by pressing Key push-button on EVAL board) the correspondent interruptis served, in the ISR the led connected to PC.07 is turned off and the EXTI line9pending bit is not cleared. So the CPU will execute indefinitely EXTI line9 ISR andthe WWDG ISR will never be entered(WWDG counter not updated). As result, when theWWDG counter falls to 3Fh the WWDG reset occurs.If the EXTI line9 event don抰 occurs the WWDG counter is indefinitely refreshed inthe WWDG ISR which prevent from WWDG reset.
If the WWDG reset is Generated, after resuming from reset a led connected to PC.06is turned on.
In this example the system is clocked by the HSE(8MHz).
標(biāo)簽：
V100
STM
100
32V
上傳時間：
2013-11-11
上傳用戶：gundamwzc
-
Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat Generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
標(biāo)簽：
封裝
器件
用戶
賽靈思
上傳時間：
2013-11-21
上傳用戶：不懂夜的黑
-
Automobiles, aircraft, marine vehicles, uninterruptiblepower supplies and telecom hardware represent areasutilizing series connected battery stacks. These stacksof individual cells may contain many units, reaching potentialsof hundreds of volts. In such systems it is oftendesirable to accurately determine each individual cell’svoltage. Obtaining this information in the presence of thehigh “common mode” voltage Generated by the batterystack is more diffi cult than might be supposed.
標(biāo)簽：
電池組
電壓
量的研究
上傳時間：
2013-10-24
上傳用戶：kang1923
-
This firmware translates a PS/2 mouse to a USB mouse. The translator
firmware is entirely interrupt driven (with the exception of sending the
data via USB to the host.) An interrupt is Generated when the PS/2 start
bit is received, at which time the firmware will begin its receive routine.
In addition to this interrupt, every 168ms a timer overflow interrupts the
main program and implements one state of the mouse state machine. This
state machine handles sending bytes to and translating bytes received from
the PS/2 mouse automatically. All of this is done in the background while
the main program runs in the foreground. The only operation that the main
program implements is sending mouse data to the PC via USB.
標(biāo)簽：
firmware
mouse
translates
translator
上傳時間：
2015-04-26
上傳用戶：cuiyashuo
