In a recent discussion with a system designer, the requirementfor his power supply was to regulate 1.5Vand deliver up to 40A of current to a load that consistedof four FPGAs. This is up to 60W of power that must bedelivered in a small area with the lowest height profi lepossible to allow a steady fl ow of air for cooling. Thepower supply had to be surface mountable and operateat high enough effi ciency to minimize heat dissipation.He also demanded the simplest possible solution so histime could be dedicated to the more complex tasks. Asidefrom precise electrical performance, this solution had toremovethe heat generated during DC to DC conversionquickly so that the circuit and the ICs in the vicinity do notoverheat. Such a solution requires an innovative designto meet these criteria:
標(biāo)簽： FPGA DCDC 集成 穩(wěn)壓器
上傳時(shí)間： 2013-11-24
上傳用戶：defghi010
Photomultipliers (PMT), avalanche photodiodes (APD),ultrasonic transducers, capacitance microphones, radiationdetectors and similar devices require high voltage,low current bias. Additionally, the high voltage must bepristinely free of noise; well under a millivolt is a commonrequirement with a few hundred microvolts sometimesnecessary. Normally, switching regulator confi gurationscannot achieve this performance level without employingspecial techniques. One aid to achieving low noise is thatload currents rarely exceed 5mA. This freedom permitsoutput fi ltering methods that are usually impractical
標(biāo)簽： DCDC 高電壓 低噪音 轉(zhuǎn)換器
上傳時(shí)間： 2013-10-28
上傳用戶：lhw888
數(shù)字控制的交流調(diào)速系統(tǒng)所選用的微處理器、功率器件及產(chǎn)生PWM波的方法是影響交流調(diào)速系統(tǒng)性能好壞的直接因素。在介紹了正弦脈寬調(diào)制(SPWM)技術(shù)的基礎(chǔ)上，設(shè)計(jì)了一種以8098單片機(jī)作為控制器，以智能功率模塊IPM為開(kāi)關(guān)器件的變頻調(diào)速系統(tǒng)。通過(guò)軟件編程，產(chǎn)生正弦脈沖寬度調(diào)制波形來(lái)控制絕緣柵雙極晶體管的導(dǎo)通和關(guān)斷，從而達(dá)到控制異步電動(dòng)機(jī)轉(zhuǎn)速的目的。實(shí)驗(yàn)結(jié)果表明，該系統(tǒng)可調(diào)頻率調(diào)電壓，穩(wěn)定度高，調(diào)速范圍寬，具有較強(qiáng)的實(shí)用價(jià)值 Abstract: AC variable speed with digital control systems used microprocessors， power devices and generate PWM wave is the direct factors of affecting the performance AC speed regulation system. On the basis of introducing the sinusoidal pulse width modulation (SPWM) technology，this paper designed variable speed system which used 8098 as a controller， intelligent power module IPM as switching device. Through software programming， resulting in sinusoidal pulse width modulation waveform to control the insulated gate bipolar transistor turn on and off， so as to achieve the purpose of speed control of induction motors. Experimental results show that the system can adjust frequency modulation voltage， high stability， wide speed range， has a strong practical value.
標(biāo)簽： 8098 SPWM 單片機(jī) 變頻調(diào)速系統(tǒng)
上傳時(shí)間： 2013-11-14
上傳用戶：ynwbosss
為解決傳統(tǒng)可視倒車(chē)?yán)走_(dá)視頻字符疊加器結(jié)構(gòu)復(fù)雜，可靠性差，成本高昂等問(wèn)題，在可視倒車(chē)?yán)走_(dá)設(shè)計(jì)中采用視頻字符發(fā)生器芯片MAX7456。該芯片集成了所有用于產(chǎn)生用戶定義OSD，并將其插入視頻信號(hào)中所需的全部功能，僅需少量的外圍阻容元件即可正常工作。給出了以MAX7456為核心的可視倒車(chē)?yán)走_(dá)的軟、硬件實(shí)現(xiàn)方案及設(shè)計(jì)實(shí)例。該方案具有電路結(jié)構(gòu)簡(jiǎn)單、價(jià)格低廉、符合人體視覺(jué)習(xí)慣的特點(diǎn)。經(jīng)實(shí)際裝車(chē)測(cè)試，按該方案設(shè)計(jì)的可視倒車(chē)?yán)走_(dá)視場(chǎng)清晰、提示字符醒目、工作可靠，可有效降低駕駛員倒車(chē)時(shí)的工作強(qiáng)度、減少倒車(chē)事故的發(fā)生。 Abstract: A new video and text generation chip，MAX7456，was used in the design of video parking sensor in order to simplify system structure，improve reliability and reduce cost. This chip included all the necessary functions to generate user-defined OSDs and to add them into the video signals. It could be put into work with addition of just a small number of resistances and capacitors. This paper provided software and hardware implementation solutions and design example based on the chip. The system had the characteristics of simplicity in circuit structure，lower cost，and comfort for the nature of human vision. Loading road test demonstrates high video and text display quality and reliable performance，which makes the driver easy to see backward and reduces chance of accidents.
標(biāo)簽： 7456 MAX 可視倒車(chē) 中的應(yīng)用
上傳時(shí)間： 2013-12-10
上傳用戶：qiaoyue
NXP Semiconductor designed the LPC2400 microcontrollers around a 16-bit/32-bitARM7TDMI-S CPU core with real-time debug interfaces that include both JTAG andembedded Trace. The LPC2400 microcontrollers have 512 kB of on-chip high-speedFlash memory. This Flash memory includes a special 128-bit wide memory interface andaccelerator architecture that enables the CPU to execute sequential instructions fromFlash memory at the maximum 72 MHz system clock rate. This feature is available onlyon the LPC2000 ARM Microcontroller family of products. The LPC2400 can execute both32-bit ARM and 16-bit Thumb instructions. Support for the two Instruction Sets meansEngineers can choose to optimize their application for either performance or code size atthe sub-routine level. When the core executes instructions in Thumb state it can reducecode size by more than 30 % with only a small loss in performance while executinginstructions in ARM state maximizes core performance.
上傳時(shí)間： 2013-11-15
上傳用戶：zouxinwang
The TJA1042 is a high-speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol controller and the physical two-wire CAN bus.The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing the differential transmit and receive capability to (amicrocontroller with) a CAN protocol controller.
標(biāo)簽： High-speed transce 1042 TJA
上傳時(shí)間： 2014-12-28
上傳用戶：氣溫達(dá)上千萬(wàn)的
The TJA1051 is a high-speed CAN transceiver that provides an interface between aController Area Network (CAN) protocol controller and the physical two-wire CAN bus.The transceiver is designed for high-speed (up to 1 Mbit/s) CAN applications in theautomotive industry, providing differential transmit and receive capability to (amicrocontroller with) a CAN protocol controller.
標(biāo)簽： High-speed transce 1051 TJA
上傳時(shí)間： 2013-10-17
上傳用戶：jisujeke
基于單片機(jī)的除塵控制器的設(shè)計(jì):介紹通用控制儀的硬件組成和軟件設(shè)計(jì),闡述了系統(tǒng)的性能指標(biāo)和功能特點(diǎn)。該產(chǎn)品功能完善,可靠性高,具有很好的應(yīng)用前景。關(guān)鍵詞: 除塵器;通用控制儀;單片機(jī);系統(tǒng)設(shè)計(jì) Abstract: The hardware structure and the software design are introduced in this paper, and the performance index and the features of the system are expounded. It has comp rehensive functions, high reliability and good app lication.Key words: dust catcher; universal controller; microcontroller; system design
上傳時(shí)間： 2013-11-16
上傳用戶：ming52900
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標(biāo)簽： UltraScale Xilinx 架構(gòu)
上傳時(shí)間： 2013-11-13
上傳用戶：瓦力瓦力hong
Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
上傳時(shí)間： 2013-10-22
上傳用戶：ztj182002
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