特點 精確度0.1%滿刻度 ±1位數 顯示范圍-19999-99999可任意規劃 可直接量測直流電流/直流電壓,無需另接輔助電源 尺寸小(24x48x50mm),穩定性高 分離式端子,配線容易 CE 認證 2.主要規格 輔助電源: None 精確度: 0.1% F.S. ±1 digit(1-100%F.S.) 輸入抗阻 : >100Mohm(<2V range) >2Mohm(<2Vrange) < 0.25VA(current ranges) < 1000Vrms(>54V ranges) 最大過載能力: < 150Vrms(<54V ranges)
上傳時間： 2013-10-08
上傳用戶：tiantwo
Abstract: Field-programmable gate arrays (FPGAs) are used in a wide variety of applications and end markets, including digital signalprocessing, medical imaging, and high-performance computing. This application note outlines the issues related to powering FPGAs.It also discusses Maxim's solutions for powering Xilinx® FPGAs.
上傳時間： 2013-12-16
上傳用戶：haohaoxuexi
The use of the Wind River VxWorks Real-Time Operating System (RTOS) on Virtex™-4embedded PowerPC™ processors continues to be a popular choice for high performanceFPGA designs. The introduction of the Wind River Workbench design environment has enableda new and easier way for designers to control the configuration of the VxWorks kernel. Thisguide shows the steps required to build and configure a ML403 Embedded DevelopmentPlatform to boot and run the VxWorks RTOS. A VxWorks bootloader is created, programmedinto Flash, and used to boot the design. The concepts presented here can be scaled to anyPowerPC enabled development platform.
上傳時間： 2013-10-26
上傳用戶：agent
The NCV7356 is a physical layer device for a single wire data linkcapable of operating with various Carrier Sense Multiple Accesswith Collision Resolution (CSMA/CR) protocols such as the BoschController Area Network (CAN) version 2.0. This serial data linknetwork is intended for use in applications where high data rate is notrequired and a lower data rate can achieve cost reductions in both thephysical media components and in the microprocessor and/ordedicated logic devices which use the network.The network shall be able to operate in either the normal data ratemode or a high-speed data download mode for assembly line andservice data transfer operations. The high-speed mode is onlyintended to be operational when the bus is attached to an off-boardservice node. This node shall provide temporary bus electrical loadswhich facilitate higher speed operation. Such temporary loads shouldbe removed when not performing download operations.The bit rate for normal communications is typically 33 kbit/s, forhigh-speed transmissions like described above a typical bit rate of83 kbit/s is recommended. The NCV7356 features undervoltagelockout, timeout for faulty blocked input signals, output blankingtime in case of bus ringing and a very low sleep mode current.
上傳時間： 2013-10-24
上傳用戶：s藍莓汁
The LPC2292/2294 microcontrollers are based on a 16/32-bit ARM7TDMI-S CPU with real-time emulation and embedded trace support, together with 256 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct with minimal performance penalty. With their 144-pin package, low power consumption, various 32-bit timers, 8-channel 10-bit ADC, 2/4 (LPC2294) advanced CAN channels, PWM channels and up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control applications as well as medical systems and fault-tolerant maintenance buses. The number of available fast GPIOs ranges from 76 (with external memory) through 112 (single-chip). With a wide range of additional serial communications interfaces, they are also suited for communication gateways and protocol converters as well as many other general-purpose applications. Remark: Throughout the data sheet, the term LPC2292/2294 will apply to devices with and without the /00 or /01 suffix. The suffixes /00 and /01 will be used to differentiate from other devices only when necessary.
上傳時間： 2014-12-30
上傳用戶：aysyzxzm
Abstract: High-speed and low-speed data converters serve critical functions in modern broadband mobile radios. This application note outlines how todetermine high-speed data converter performance requirements in baseband sampling radio architectures. Also, system partition strategies andadvantages are outlined when considering a high-speed analog front-end (AFE) solution.
上傳時間： 2013-11-02
上傳用戶：jjj0202
We offer a broad line of high performance low dropout (LDO) linear regulators with fasttransient response, excellent line and load regulation, and very wide input voltage rangefrom 0.9V to 100V. Output currents range from 20mA to 10A, with positive, negative andmultiple output versions available. Many devices offer output voltage operation <0.8V andsome feature operation as low as 0V, even with a single supply. Most are stable with ceramicoutput capacitors. LDO regulators can be applied in virtually any application.
上傳時間： 2013-11-15
上傳用戶：努力努力再努力
為了能夠滿足基站易于選址、優質快速的建站要求和易維護、低成本、高可靠的運行要求，本文對以方艙來實現一體化結構基站做出一番探討。從系統設計的觀點闡述了移動通信高性能基站天線設計的幾個關鍵問題，介紹了智能天線技術在基站中的應用，并且用HFSS軟件仿真了一種新型的對稱陣子天線，該天線駐波比小于2的帶寬可以達到60%，具有良好的寬頻帶特性。 Abstract: In order to meet the station construction requirement of easy site selection and fast base station， and meet the operational requirement of easy maintenance， low cost and high reliability， this paper discussed the unified architecture base station using shelter. Several key problems of high performance mobile communication base station antenna were illustrated from the view of system design， the application of smart antenna in base station was also introduced. And a novel dipole antenna was simulated by using HFSS， the VSWR of the antenna is less than 2， and the bandwidth was reach to 60%. So it has good broadband properties.
上傳時間： 2013-11-20
上傳用戶：linlin
針對UHF讀寫器設計中，在符合EPC Gen2標準的情況下，對標簽返回的高速數據進行正確解碼以達到正確讀取標簽的要求，提出了一種新的在ARM平臺下采用邊沿捕獲統計定時器數判斷數據的方法，并對FM0編碼進行解碼。與傳統的使用定時器定時采樣高低電平的FM0解碼方法相比，該解碼方法可以減少定時器定時誤差累積的影響；可以將捕獲定時器數中斷與數據判斷解碼相對分隔開，使得中斷對解碼影響很小，實現捕獲與解碼的同步。通過實驗表明，這種方法提高了解碼的效率，在160 Kb/s的接收速度下，讀取一張標簽的時間約為30次/s。 Abstract: Aiming at the requirement of receiving correctly decoded data from the tag under high-speed communication which complied with EPC Gen2 standard in the design of UHF interrogator， the article introduced a new technology for FM0 decoding which counted the timer counter to judge data by using the edge interval of signal capture based on the ARM7 platform. Compared with the traditional FM0 decoding method which used the timer timed to sample the high and low level， the method could reduce the accumulation of timing error and could relatively separate capture timer interrupt and the data judgment for decoding， so that the disruption effect on the decoding was small and realizd synchronization of capture and decoding. Testing result shows that the method improves the efficiency of decoding， at 160 Kb/s receiving speed， the time of the interrogator to read a tag is about 30 times/s.
上傳時間： 2013-11-10
上傳用戶：liufei
Agilent AN 154 S-Parameter Design Application Note S參數的設計與應用 The need for new high-frequency, solid-state circuitdesign techniques has been recognized both by microwaveengineers and circuit designers. These engineersare being asked to design solid state circuitsthat will operate at higher and higher frequencies.The development of microwave transistors andAgilent Technologies’ network analysis instrumentationsystems that permit complete network characterizationin the microwave frequency rangehave greatly assisted these engineers in their work.The Agilent Microwave Division’s lab staff hasdeveloped a high frequency circuit design seminarto assist their counterparts in R&D labs throughoutthe world. This seminar has been presentedin a number of locations in the United States andEurope.From the experience gained in presenting this originalseminar, we have developed a four-part videotape, S-Parameter Design Seminar. While the technologyof high frequency circuit design is everchanging, the concepts upon which this technologyhas been built are relatively invariant.The content of the S-Parameter Design Seminar isas follows:
標簽： S參數
上傳時間： 2013-12-19
上傳用戶：aa54
