Multioutput monolithic regulators are easy to use and fi tinto spaces where multichip solutions cannot. Nevertheless,the popularity of multioutput regulators is temperedby a lack of options for input voltages above 30V andsupport of high output currents. The LT3692A fi lls thisgap with a dual monolithic regulator that operates frominputs up to 36V. It also includes a number of channeloptimization features that allow the LT3692A’s per-channelperformance to rival that of multichip solutions.
上傳時間： 2014-01-03
上傳用戶：Huge_Brother
The RT9018A/B is a high performance positive voltage regulator designed for use in applications requining very low Input voltage and very low dropout voltage at up to 3A(peak).
上傳時間： 2013-10-10
上傳用戶：geshaowei
The NXP LPC314x combine a 270 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, three channel10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted atconsumer, industrial, medical, and communication markets. To optimize system powerconsumption, the LPC314x have multiple power domains and a very flexible ClockGeneration Unit (CGU) that provides dynamic clock gating and scaling.
上傳時間： 2013-10-11
上傳用戶：yuchunhai1990
The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals. The ARMCortex-M3 CPU also includes an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM data memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external memory controller, and multiple digital andanalog peripherals.
上傳時間： 2014-12-31
上傳用戶：zhuoying119
The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andincludes an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
上傳時間： 2013-10-28
上傳用戶：15501536189
The NXP LPC315x combine an 180 MHz ARM926EJ-S CPU core, High-speed USB 2.0OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, an integratedaudio codec, Li-ion charger, Real-Time Clock (RTC), and a myriad of serial and parallelinterfaces in a single chip targeted at consumer, industrial, medical, and communicationmarkets. To optimize system power consumption, the LPC315x have multiple powerdomains and a very flexible Clock Generation Unit (CGU) that provides dynamic clockgating and scaling.The LPC315x is implemented as multi-chip module with two side-by-side dies, one fordigital fuctions and one for analog functions, which include a Power Supply Unit (PSU),audio codec, RTC, and Li-ion battery charger.
上傳時間： 2014-01-17
上傳用戶：Altman
The super-junction structure, which has P-type pillar layers as shown left, realizes high withstand voltage and ON-resistance lower than the conventional theoretical limit of silicon.
上傳時間： 2014-12-31
上傳用戶：qwer0574
注:1.這篇文章斷斷續續寫了很久,畫圖技術也不精,難免錯漏,大家湊合看.有問題可以留言. 2.論壇排版把我的代碼縮進全弄沒了,大家將代碼粘貼到arduino編譯器,然后按ctrl+T重新格式化代碼格式即可看的舒服. 一、什么是PWM PWM 即Pulse Wavelength Modulation 脈寬調制波，通過調整輸出信號占空比，從而達到改 變輸出平均電壓的目的。相信Arduino 的PWM 大家都不陌生，在Arduino Duemilanove 2009 中，有6 個8 位精度PWM 引腳，分別是3, 5, 6, 9, 10, 11 腳。我們可以使用analogWrite()控 制PWM 腳輸出頻率大概在500Hz 的左右的PWM 調制波。分辨率8 位即2 的8 次方等于 256 級精度。但是有時候我們會覺得6 個PWM 引腳不夠用。比如我們做一個10 路燈調光， 就需要有10 個PWM 腳。Arduino Duemilanove 2009 有13 個數字輸出腳，如果它們都可以 PWM 的話，就能滿足條件了。于是本文介紹用軟件模擬PWM。 二、Arduino 軟件模擬PWM Arduino PWM 調壓原理：PWM 有好幾種方法。而Arduino 因為電源和實現難度限制，一般 使用周期恒定，占空比變化的單極性PWM。 通過調整一個周期里面輸出腳高/低電平的時間比（即是占空比）去獲得給一個用電器不同 的平均功率。 如圖所示，假設PWM 波形周期1ms（即1kHz），分辨率1000 級。那么需要一個信號時間 精度1ms/1000=1us 的信號源，即1MHz。所以說，PWM 的實現難點在于需要使用很高頻的 信號源，才能獲得快速與高精度。下面先由一個簡單的PWM 程序開始： const int PWMPin = 13; int bright = 0; void setup() { pinMode(PWMPin, OUTPUT); } void loop() { if((bright++) == 255) bright = 0; for(int i = 0; i < 255; i++) { if(i < bright) { digitalWrite(PWMPin, HIGH); delayMicroseconds(30); } else { digitalWrite(PWMPin, LOW); delayMicroseconds(30); } } } 這是一個軟件PWM 控制Arduino D13 引腳的例子。只需要一塊Arduino 即可測試此代碼。 程序解析：由for 循環可以看出，完成一個PWM 周期，共循環255 次。 假設bright=100 時候，在第0~100 次循環中，i 等于1 到99 均小于bright，于是輸出PWMPin 高電平； 然后第100 到255 次循環里面，i 等于100~255 大于bright，于是輸出PWMPin 低電平。無 論輸出高低電平都保持30us。 那么說，如果bright=100 的話，就有100 次循環是高電平，155 次循環是低電平。 如果忽略指令執行時間的話，這次的PWM 波形占空比為100/255，如果調整bright 的值， 就能改變接在D13 的LED 的亮度。 這里設置了每次for 循環之后，將bright 加一，并且當bright 加到255 時歸0。所以，我們 看到的最終效果就是LED 慢慢變亮，到頂之后然后突然暗回去重新變亮。 這是最基本的PWM 方法，也應該是大家想的比較多的想法。 然后介紹一個簡單一點的。思維風格完全不同。不過對于驅動一個LED 來說，效果與上面 的程序一樣。 const int PWMPin = 13; int bright = 0; void setup() { pinMode(PWMPin, OUTPUT); } void loop() { digitalWrite(PWMPin, HIGH); delayMicroseconds(bright*30); digitalWrite(PWMPin, LOW); delayMicroseconds((255 - bright)*30); if((bright++) == 255) bright = 0; } 可以看出，這段代碼少了一個For 循環。它先輸出一個高電平，然后維持(bright*30)us。然 后輸出一個低電平，維持時間((255-bright)*30)us。這樣兩次高低就能完成一個PWM 周期。 分辨率也是255。 三、多引腳PWM Arduino 本身已有PWM 引腳并且運行起來不占CPU 時間，所以軟件模擬一個引腳的PWM 完全沒有實用意義。我們軟件模擬的價值在于：他能將任意的數字IO 口變成PWM 引腳。 當一片Arduino 要同時控制多個PWM，并且沒有其他重任務的時候，就要用軟件PWM 了。 多引腳PWM 有一種下面的方式： int brights[14] = {0}; //定義14個引腳的初始亮度，可以隨意設置 int StartPWMPin = 0, EndPWMPin = 13; //設置D0~D13為PWM 引腳 int PWMResolution = 255; //設置PWM 占空比分辨率 void setup() { //定義所有IO 端輸出 for(int i = StartPWMPin; i <= EndPWMPin; i++) { pinMode(i, OUTPUT); //隨便定義個初始亮度,便于觀察 brights[ i ] = random(0, 255); } } void loop() { //這for 循環是為14盞燈做漸亮的。每次Arduino loop()循環， //brights 自增一次。直到brights=255時候，將brights 置零重新計數。 for(int i = StartPWMPin; i <= EndPWMPin; i++) { if((brights[i]++) == PWMResolution) brights[i] = 0; } for(int i = 0; i <= PWMResolution; i++) //i 是計數一個PWM 周期 { for(int j = StartPWMPin; j <= EndPWMPin; j++) //每個PWM 周期均遍歷所有引腳 { if(i < brights[j])\ 所以我們要更改PWM 周期的話，我們將精度（代碼里面的變量：PWMResolution）降低就行，比如一般調整LED 亮度的話，我們用64 級精度就行。這樣速度就是2x32x64=4ms。就不會閃了。
上傳時間： 2013-10-08
上傳用戶：dingdingcandy
超聲波傳感器適用于對大幅的平面進行靜止測距。普通的超聲波傳感器測距范圍大概是 2cm~450cm，分辨率3mm（淘寶賣家說的，筆者測試環境沒那么好，個人實測比較穩定的 距離10cm~2m 左右，超過此距離就經常有偶然不準確的情況發生了，當然不排除筆者技術 問題。） 測試對象是淘寶上面最便宜的SRF-04 超聲波傳感器，有四個腳：5v 電源腳（Vcc），觸發控制端（Trig），接收端（Echo），地端（GND） 附:SRF 系列超聲波傳感器參數比較 模塊工作原理： 采用IO 觸發測距，給至少10us 的高電平信號； 模塊自動發送8個40KHz 的方波，自動檢測是否有信號返回； 有信號返回，通過IO 輸出一高電平，高電平持續的時間就是超聲波從發射到返回的時間．測試距離=(高電平時間*聲速(340m/s))/2; 電路連接方法 Arduino 程序例子： constintTrigPin = 2; constintEchoPin = 3; floatcm; voidsetup() { Serial.begin(9600); pinMode(TrigPin, OUTPUT); pinMode(EchoPin, INPUT); } voidloop() { digitalWrite(TrigPin, LOW); //低高低電平發一個短時間脈沖去TrigPin delayMicroseconds(2); digitalWrite(TrigPin, HIGH); delayMicroseconds(10); digitalWrite(TrigPin, LOW); cm = pulseIn(EchoPin, HIGH) / 58.0; //將回波時間換算成cm cm = (int(cm * 100.0)) / 100.0; //保留兩位小數 Serial.print(cm); Serial.print("cm"); Serial.println(); delay(1000); }
上傳時間： 2013-10-18
上傳用戶：星仔
中文版詳情瀏覽：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
標簽： UltraScale Xilinx 架構
上傳時間： 2013-11-21
上傳用戶：wxqman
