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Multioutput monolithic regulators are easy to use and fi tinto spaces where multichip solutions cannot. Nevertheless,the popularity of multioutput regulators is temperedby a lack of options for input voltages above 30V andsupport of high output currents. The LT3692A fi lls thisgap with a dual monolithic regulator that operates frominputs up to 36V. It also INCLUDEs a number of channeloptimization features that allow the LT3692A’s per-channelperformance to rival that of multichip solutions.
標(biāo)簽：
492
DN
降壓
溫度監(jiān)控
上傳時(shí)間：
2014-01-03
上傳用戶：Huge_Brother
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The LPC1850/30/20/10 are ARM Cortex-M3 based microcontrollers for embeddedapplications. The ARM Cortex-M3 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC1850/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals. The ARMCortex-M3 CPU also INCLUDEs an internal prefetch unit that supports speculativebranching.The LPC1850/30/20/10 include up to 200 kB of on-chip SRAM data memory, a quad SPIFlash Interface (SPIFI), a State Configuration Timer (SCT) subsystem, two High-speedUSB controllers, Ethernet, LCD, an external memory controller, and multiple digital andanalog peripherals.
標(biāo)簽：
Cortex-M
1850
LPC
內(nèi)核微控制器
上傳時(shí)間：
2014-12-31
上傳用戶：zhuoying119
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The LPC4350/30/20/10 are ARM Cortex-M4 based microcontrollers for embeddedapplications. The ARM Cortex-M4 is a next generation core that offers systemenhancements such as low power consumption, enhanced debug features, and a highlevel of support block integration.The LPC4350/30/20/10 operate at CPU frequencies of up to 150 MHz. The ARMCortex-M4 CPU incorporates a 3-stage pipeline, uses a Harvard architecture withseparate local instruction and data buses as well as a third bus for peripherals, andINCLUDEs an internal prefetch unit that supports speculative branching. The ARMCortex-M4 supports single-cycle digital signal processing and SIMD instructions. Ahardware floating-point processor is integrated in the core.The LPC4350/30/20/10 include an ARM Cortex-M0 coprocessor, up to 264 kB of datamemory, advanced configurable peripherals such as the State Configurable Timer (SCT)and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers,Ethernet, LCD, an external memory controller, and multiple digital and analog peripherals
標(biāo)簽：
4300
LPC
ARM
雙核微控制器
上傳時(shí)間：
2013-10-28
上傳用戶：15501536189
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Nios II軟件構(gòu)建工具入門(mén)
The Nios® II Software Build Tools (SBT) allows you to construct a wide variety of
complex embedded software systems using a command-line interface. From this
interface, you can execute Software Built Tools command utilities, and use scripts
other tools) to combine the command utilities in many useful ways.
This chapter introduces you to project creation with the SBT at the command line
This chapter INCLUDEs the following sections:
■ “Advantages of Command-Line Software Development”
■ “Outline of the Nios II SBT Command-Line Interface”
■ “Getting Started in the SBT Command Line”
■ “Software Build Tools Scripting Basics” on page 3–8
標(biāo)簽：
Nios
軟件
上傳時(shí)間：
2013-11-15
上傳用戶：nanxia
-
通過(guò)以太網(wǎng)遠(yuǎn)程配置Nios II 處理器 應(yīng)用筆記
Firmware in embedded hardware systems is frequently updated over the Ethernet. For
embedded systems that comprise a discrete microprocessor and the devices it controls, the
firmware is the software image run by the microprocessor. When the embedded system
INCLUDEs an FPGA, firmware updates include updates of the hardware image on the FPGA. If
the FPGA INCLUDEs a Nios® II soft processor, you can upgrade both the Nios II processor—as
part of the FPGA image—and the software that the Nios II processor runs, in a single remote
configuration session.
標(biāo)簽：
Nios
遠(yuǎn)程
處理器
應(yīng)用筆記
上傳時(shí)間：
2013-11-22
上傳用戶：chaisz
-
This application note describes the implementation of a two-dimensional Rank Order filter. Thereference design INCLUDEs the RTL VHDL implementation of an efficient sorting algorithm. Thedesign is parameterizable for input/output precision, color standards, filter kernel size,maximum horizontal resolution, and implementation options. The rank to be selected can bemodified dynamically, and the actual horizontal resolution is picked up automatically from theinput synchronization signals. The design has a fully synchronous interface through the ce, clk,and rst ports.
標(biāo)簽：
XAPP
953
二維
濾波器
上傳時(shí)間：
2013-12-14
上傳用戶：逗逗666
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The LogiCORE™ GTP Wizard automates the task of creating HDL wrappers to configure the high-speed serial GTP transceivers in Virtex™-5 LXT and SXT devices. The menu-driven interface allows one or more GTP transceivers to be configured using pre-definedtemplates for popular industry standards, or from scratch, to support a wide variety of custom protocols.The Wizard produces a wrapper, an example design, and a testbench for rapid integration and verification of the serial interface with your custom function
Features• Creates customized HDL wrappers to configureVirtex-5 RocketIO™ GTP transceivers• Users can configure Virtex-5 GTP transceivers toconform to industry standard protocols usingpredefined templates, or tailor the templates forcustom protocols• Included protocol templates provide support for thefollowing specifications: Aurora, CPRI, FibreChannel 1x, Gigabit Ethernet, HD-SDI, OBSAI,OC3, OC12, OC48, PCI Express® (PCIe®), SATA,SATA II, and XAUI• Automatically configures analog settings• Each custom wrapper INCLUDEs example design, testbench; and both implementation and simulation scripts
標(biāo)簽：
Transceiver
Virtex
Wizar
GTP
上傳時(shí)間：
2013-10-20
上傳用戶：dave520l
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ref-sdr-sdram-vhdl代碼
SDR SDRAM Controller v1.1 readme.txt
This readme file for the SDR SDRAM Controller INCLUDEs information that was not
incorporated into the SDR SDRAM Controller White Paper v1.1.
The PLL is targeted at APEX(TM) devices. Please regenerate for your chosen architecture.
Last updated September, 2002
Copyright ?2002 Altera Corporation. All rights reserved.
標(biāo)簽：
sdram
vhdl
ref
sdr
上傳時(shí)間：
2013-10-23
上傳用戶：半熟1994
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Integrated EMI/Thermal Design forSwitching Power SuppliesWei ZhangThesis submitted to the Faculty of theVirginia Polytechnic Institute and State Universityin partial fulfillment of the requirements for the degree of
Integrated EMI/Thermal Design forSwitching Power SuppliesWei Zhang(ABSTRACT)This work presents the modeling and analysis of EMI and thermal performancefor switch power supply by using the CAD tools. The methodology and design guidelinesare developed.By using a boost PFC circuit as an example, an equivalent circuit model is builtfor EMI noise prediction and analysis. The parasitic elements of circuit layout andcomponents are extracted analytically or by using CAD tools. Based on the model, circuitlayout and magnetic component design are modified to minimize circuit EMI. EMI filtercan be designed at an early stage without prototype implementation.In the second part, thermal analyses are conducted for the circuit by using thesoftware Flotherm, which INCLUDEs the mechanism of conduction, convection andradiation. Thermal models are built for the components. Thermal performance of thecircuit and the temperature profile of components are predicted. Improved thermalmanagement and winding arrangement are investigated to reduce temperature.In the third part, several circuit layouts and inductor design examples are checkedfrom both the EMI and thermal point of view. Insightful information is obtained.
標(biāo)簽：
EMI
開(kāi)關(guān)電源
英文
上傳時(shí)間：
2013-11-16
上傳用戶：萍水相逢
-
This document provides practical, common guidelines for incorporating PCI Express interconnect
layouts onto Printed Circuit Boards (PCB) ranging from 4-layer desktop baseboard designs to 10-
layer or more server baseboard designs. Guidelines and constraints in this document are intended
for use on both baseboard and add-in card PCB designs. This INCLUDEs interconnects between PCI
Express devices located on the same baseboard (chip-to-chip routing) and interconnects between
a PCI Express device located “down” on the baseboard and a device located “up” on an add-in
card attached through a connector.
This document is intended to cover all major components of the physical interconnect including
design guidelines for the PCB traces, vias and AC coupling capacitors, as well as add-in card
edge-finger and connector considerations. The intent of the guidelines and examples is to help
ensure that good high-speed signal design practices are used and that the timing/jitter and
loss/attenuation budgets can also be met from end-to-end across the PCI Express interconnect.
However, while general physical guidelines and suggestions are given, they may not necessarily
guarantee adequate performance of the interconnect for all layouts and implementations.
Therefore, designers should consider modeling and simulation of the interconnect in order to
ensure compliance to all applicable specifications.
The document is composed of two main sections. The first section provides an overview of
general topology and interconnect guidelines. The second section concentrates on physical layout
constraints where bulleted items at the beginning of a topic highlight important constraints, while
the narrative that follows offers additional insight.
標(biāo)簽：
pci
PCB
設(shè)計(jì)規(guī)范
上傳時(shí)間：
2014-01-24
上傳用戶：s363994250
