#include<stdio.h> #define TREEMAX 100 typedef struct BT { char data; BT *lchild; BT *rchild; }BT; BT *CreateTree(); void Preorder(BT *T); void Postorder(BT *T); void Inorder(BT *T); void Leafnum(BT *T); void Nodenum(BT *T); int TreeDepth(BT *T); int count=0; void main() { BT *T=NULL; char ch1,ch2,a; ch1='y'; while(ch1=='y'||ch1=='y') { printf("\n"); printf("\n\t\t 二叉樹子系統"); printf("\n\t\t*****************************************"); printf("\n\t\t 1---------建二叉樹 "); printf("\n\t\t 2---------先序遍歷 "); printf("\n\t\t 3---------中序遍歷 "); printf("\n\t\t 4---------后序遍歷 "); printf("\n\t\t 5---------求葉子數 "); printf("\n\t\t 6---------求結點數 "); printf("\n\t\t 7---------求樹深度 "); printf("\n\t\t 0---------返 回 "); printf("\n\t\t*****************************************"); printf("\n\t\t 請選擇菜單號 (0--7)"); scanf("%c",&ch2); getchar(); printf("\n"); switch(ch2) { case'1': printf("\n\t\t請按先序序列輸入二叉樹的結點:\n"); printf("\n\t\t說明:輸入結點(‘0’代表后繼結點為空)后按回車。\n"); printf("\n\t\t請輸入根結點:"); T=CreateTree(); printf("\n\t\t二叉樹成功建立!\n");break; case'2': printf("\n\t\t該二叉樹的先序遍歷序列為:"); Preorder(T);break; case'3': printf("\n\t\t該二叉樹的中序遍歷序列為:"); Inorder(T);break; case'4': printf("\n\t\t該二叉樹的后序遍歷序列為:"); Postorder(T);break; case'5': count=0;Leafnum(T); printf("\n\t\t該二叉樹有%d個葉子。\n",count);break; case'6': count=0;Nodenum(T); printf("\n\t\t該二叉樹總共有%d個結點。\n",count);break; case'7': printf("\n\t\t該樹的深度為:%d",TreeDepth(T)); break; case'0': ch1='n';break; default: printf("\n\t\t***請注意:輸入有誤!***"); } if(ch2!='0') { printf("\n\n\t\t按【Enter】鍵繼續,按任意鍵返回主菜單!\n"); a=getchar(); if(a!='\xA') { getchar(); ch1='n'; } } } } BT *CreateTree() { BT *t; char x; scanf("%c",&x); getchar(); if(x=='0') t=NULL; else { t=new BT; t->data=x; printf("\n\t\t請輸入%c結點的左子結點:",t->data); t->lchild=CreateTree(); printf("\n\t\t請輸入%c結點的右子結點:",t->data); t->rchild=CreateTree(); } return t; } void Preorder(BT *T) { if(T) { printf("%3c",T->data); Preorder(T->lchild); Preorder(T->rchild); } } void Inorder(BT *T) { if(T) { Inorder(T->lchild); printf("%3c",T->data); Inorder(T->rchild); } } void Postorder(BT *T) { if(T) { Postorder(T->lchild); Postorder(T->rchild); printf("%3c",T->data); } } void Leafnum(BT *T) { if(T) { if(T->lchild==NULL&&T->rchild==NULL) count++; Leafnum(T->lchild); Leafnum(T->rchild); } } void Nodenum(BT *T) { if(T) { count++; Nodenum(T->lchild); Nodenum(T->rchild); } } int TreeDepth(BT *T) { int ldep,rdep; if(T==NULL) return 0; else { ldep=TreeDepth(T->lchild); rdep=TreeDepth(T->rchild); if(ldep>rdep) return ldep+1; else return rdep+1; } }
上傳時間: 2020-06-11
上傳用戶:ccccy
#include <stdio.h> #include <stdlib.h> #define SMAX 100 typedef struct SPNode { int i,j,v; }SPNode; struct sparmatrix { int rows,cols,terms; SPNode data [SMAX]; }; sparmatrix CreateSparmatrix() { sparmatrix A; printf("\n\t\t請輸入稀疏矩陣的行數,列數和非零元素個數(用逗號隔開):"); scanf("%d,%d,%d",&A.cols,&A.terms); for(int n=0;n<=A.terms-1;n++) { printf("\n\t\t輸入非零元素值(格式:行號,列號,值):"); scanf("%d,%d,%d",&A.data[n].i,&A.data[n].j,&A.data[n].v); } return A; } void ShowSparmatrix(sparmatrix A) { int k; printf("\n\t\t"); for(int x=0;x<=A.rows-1;x++) { for(int y=0;y<=A.cols-1;y++) { k=0; for(int n=0;n<=A.terms-1;n++) { if((A.data[n].i-1==x)&&(A.data[n].j-1==y)) { printf("%8d",A.data[n].v); k=1; } } if(k==0) printf("%8d",k); } printf("\n\t\t"); } } void sumsparmatrix(sparmatrix A) { SPNode *p; p=(SPNode*)malloc(sizeof(SPNode)); p->v=0; int k; k=0; printf("\n\t\t"); for(int x=0;x<=A.rows-1;x++) { for(int y=0;y<=A.cols-1;y++) { for(int n=0;n<=A.terms;n++) { if((A.data[n].i==x)&&(A.data[n].j==y)&&(x==y)) { p->v=p->v+A.data[n].v; k=1; } } } printf("\n\t\t"); } if(k==1) printf("\n\t\t對角線元素的和::%d\n",p->v); else printf("\n\t\t對角線元素的和為::0"); } int main() { int ch=1,choice; struct sparmatrix A; A.terms=0; while(ch) { printf("\n"); printf("\n\t\t 稀疏矩陣的三元組系統 "); printf("\n\t\t*********************************"); printf("\n\t\t 1------------創建 "); printf("\n\t\t 2------------顯示 "); printf("\n\t\t 3------------求對角線元素和"); printf("\n\t\t 4------------返回 "); printf("\n\t\t*********************************"); printf("\n\t\t請選擇菜單號(0-3):"); scanf("%d",&choice); switch(choice) { case 1: A=CreateSparmatrix(); break; case 2: ShowSparmatrix(A); break; case 3: SumSparmatrix(A); break; default: system("cls"); printf("\n\t\t輸入錯誤!請重新輸入!\n"); break; } if (choice==1||choice==2||choice==3) { printf("\n\t\t"); system("pause"); system("cls"); } else system("cls"); } }
上傳時間: 2020-06-11
上傳用戶:ccccy
Research on microwave power amplififiers has gained a growing importance demanded by the many continuously developing applications which require such subsystem performance. A broad set of commercial and strategic systems in fact have their overall performance boosted by the power amplififier, the latter becoming an enabling component wherever its effificiency and output power actually allows functionalities and operating modes previously not possible. This is the case for the many wireless systems and battery-operated systems that form the substrate of everyday life, but also of high-performance satellite and dual-use systems.
上傳時間: 2021-10-30
上傳用戶:得之我幸78
MAX30102芯片心率血氧傳感器模塊傳感器模塊軟硬件設計資料包括STM32測試源碼AD設計原理圖及心率及血氧參考設計資料:參考代碼及實驗數據工程文件及庫心率及血氧參考設計資料芯片數據手冊1771.pdf2ES Teck PEMS White Paper.pdf31930_accessories.pdf5273c08fe2b6b_1_4264142A_EN_p.pdfAvant 2120 Brochure.pdfcelyon-1057-daeg.pdfDr. Bob case study for dental.pdfenvitec.pdfgclarke-2015-MASc-thesis.pdfiadt02i4p261.pdfIHE_PCD_Suppl_POI.pdfijcsit2014050679.pdfIMECS2009_pp1537-1540.pdfLuksSwensonPulseOximetryatHighAltitude.pdfMI_CCHD_Screener_Tips_Flier_3-21-13_422078_7.pdfMoon.pdfnotes6.pdfpansw_spo2_sensor.pdfPK_EN_MAsimo2008Product Catalog.pdfpm-60a-spo2-report-4.pdfpulse-oximetry-at-home.pdfpulse-oximetry.pdfpulse.pdfPulseOxFinal_low.pdfpulse_ox.pdfpxc3976461.pdfReusable SpO2 Sensors.pdfSP02-cross-reference-sensor.pdfsprt533.pdfsszb140.pdfview.pdf
上傳時間: 2021-11-24
上傳用戶:fliang
常用芯片表貼芯片表貼電阻電容STM封裝庫AD庫(ATIUM PCB封裝庫):PCB Library : 常用芯片表貼芯片表貼電阻電容STM封裝庫AD庫(ATIUM PCB封裝庫).PcbLibDate : 2021/5/14Time : 16:14:01Component Count : 463Component Name-----------------------------------------------LC-12-DIPH-300LC-0201LC-0201_CLC-0201_LLC-0201_RLC-0402LC-0402_CLC-0402_LLC-0402_RLC-0402_Rx2LC-0402_Rx4LC-0603LC-0603_CLC-0603_Cx4LC-0603_LLC-0603_LEDLC-0603_RLC-0603_Rx2LC-0603_Rx4LC-0805LC-0805_CLC-0805_LLC-0805_LEDLC-0805_RLC-1206LC-1206_CLC-1206_LLC-1206_RLC-1210LC-1210_CLC-1210_RLC-1806LC-1806_CLC-1806_LLC-1806_RLC-1808LC-1808_CLC-1808_LLC-1808_RLC-1812LC-1812_CLC-1812_LLC-1812_RLC-1825LC-1825_CLC-1825_LLC-1825_RLC-2010LC-2010_CLC-2010_LLC-2010_RLC-2220LC-2220_CLC-2220_LLC-2220_RLC-2225LC-2225_CLC-2225_RLC-2512LC-2512_CLC-2512_LLC-2512_RLC-ABSLC-BGA-14LC-BGA-84_7.5x12.5mmLC-BGA-121LC-BGA-143LC-BR-3LC-BR-6LC-BR-10LC-CASE 017AA-01LC-CASE-A_3216LC-CASE-B_3528LC-CASE-C_6032LC-CASE-D_7343LC-CASE-E_7343LC-CASE-P_2012LC-CASE-R_2012LC-DBLC-DBSLC-DFN-2LLC-DFN-8_3x3mmLC-DFN-8_5x6mmLC-DFN-10_3x3mmLC-DFN-10_EP_3x3mmLC-DIP-4LC-DIP-5LC-DIP-6LC-DIP-7LC-DIP-8LC-DIP-14LC-DIP-16LC-DIP-18LC-DIP-20LC-DIP-24_300milLC-DIP-24_600milLC-DIP-28_300milLC-DIP-28_600milLC-DIP-40LC-DO-15LC-DO-27LC-DO-35LC-DO-41LC-DO-201ADLC-DO-213AALC-DO-213ABLC-DO-218ABLC-DSON-10LC-FBGA-84_9x12.5mmLC-FBGA-96_8x14mmLC-FBGA-256LC-FBGA-272LC-FBGA-289LC-FBGA-484LC-FBGA-780LC-GBJLC-GBULC-GDTs_SMDLC-GDTs_THTLC-HC-49SLC-HC-49SMDLC-HC-49ULC-HTSSOP-32LC-HVMDIPLC-HVQFN-32_5x5x05PLC-HZIP25-P-1.27LC-KBJLC-KBLLC-KBPLC-KBPCLC-KBULC-LBSLC-LFBGA-217LC-LFCSP-8_3x2x05PLC-LFCSP-8_3x3x05PLC-LFCSP-16_4x4x05PLC-LFCSP-20_4x4x05PLC-LFCSP-24_4x4x05PLC-LFCSP-28_5x5x05PLC-LFCSP40_6x6x05PLC-LFCSP56_8x8x05PLC-LGA-8_3x5mmLC-LGA-14_3x5mmLC-LGA-16_3x3mmLC-LGA-16_4x4mmLC-LL-34LC-LL-35LC-LL-41LC-LPCC-148LC-LQFP-32_7x7x08PLC-LQFP-44_10x10x08PLC-LQFP-48_7x7x05P
上傳時間: 2021-12-02
上傳用戶:
FPGA片內FIFO讀寫測試Verilog邏輯源碼Quartus工程文件+文檔說明,使用 FPGA 內部的 FIFO 以及程序對該 FIFO 的數據讀寫操作。FPGA型號Cyclone4E系列中的EP4CE6F17C8,Quartus版本17.1。timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////module fifo_test( input clk, //50MHz時鐘 input rst_n //復位信號,低電平有效 );//-----------------------------------------------------------localparam W_IDLE = 1;localparam W_FIFO = 2; localparam R_IDLE = 1;localparam R_FIFO = 2; reg[2:0] write_state;reg[2:0] next_write_state;reg[2:0] read_state;reg[2:0] next_read_state;reg[15:0] w_data; //FIFO寫數據wire wr_en; //FIFO寫使能wire rd_en; //FIFO讀使能wire[15:0] r_data; //FIFO讀數據wire full; //FIFO滿信號 wire empty; //FIFO空信號 wire[8:0] rd_data_count; wire[8:0] wr_data_count; ///產生FIFO寫入的數據always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) write_state <= W_IDLE; else write_state <= next_write_state;endalways@(*)begin case(write_state) W_IDLE: if(empty == 1'b1) //FIFO空, 開始寫FIFO next_write_state <= W_FIFO; else next_write_state <= W_IDLE; W_FIFO: if(full == 1'b1) //FIFO滿 next_write_state <= W_IDLE; else next_write_state <= W_FIFO; default: next_write_state <= W_IDLE; endcaseendassign wr_en = (next_write_state == W_FIFO) ? 1'b1 : 1'b0; always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) w_data <= 16'd0; else if (wr_en == 1'b1) w_data <= w_data + 1'b1; else w_data <= 16'd0; end///產生FIFO讀的數據always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) read_state <= R_IDLE; else read_state <= next_read_state;endalways@(*)begin case(read_state) R_IDLE: if(full == 1'b1) //FIFO滿, 開始讀FIFO next_read_state <= R_FIFO; else next_read_state <= R_IDLE; R_FIFO: if(empty == 1'b1)
上傳時間: 2021-12-19
上傳用戶:20125101110
電子書-RTL Design Style Guide for Verilog HDL540頁A FF having a fixed input value is generated from the description in the upper portion of Example 2-21. In this case, ’0’ is output when the reset signal is asynchronously input, and ’1’ is output when the START signal rises. Therefore, the FF data input is fixed at the power supply, since the typical value ’1’ is output following the rise of the START signal. When FF input values are fixed, the fixed inputs become untestable and the fault detection rate drops. When implementing a scan design and converting to a scan FF, the scan may not be executed properl not be executed properly, so such descriptions , so such descriptions are not are not recommended. recommended.[1] As in the lower part of Example 2-21, be sure to construct a synchronous type of circuit and ensure that the clock signal is input to the clock pin of the FF. Other than the sample shown in Example 2-21, there are situations where for certain control signals, those that had been switched due to the conditions of an external input will no longer need to be switched, leaving only a FF. If logic exists in a lower level and a fixed value is input from an upper level, the input value of the FF may also end up being fixed as the result of optimization with logic synthesis tools. In a situation like this, while perhaps difficult to completely eliminate, the problem should be avoided as much as possible.
標簽: RTL verilog hdl
上傳時間: 2022-03-21
上傳用戶:canderile
設計了自動控制系統綜合實驗案例“基于LabVIEW和單片機的溫度控制系統設計”。實驗系統硬件部分由單片機、溫度傳感器、D/A轉換模塊、調壓模塊和電烤箱組成,設計了單片機與各個模塊之間的接口電路。軟件部分采用LabVIEW軟件實現控制算法,并設計監控界面實現參數設定、溫度數據實時監控等功能。設計了單片機與LabVIEW軟件之間的串口通信程序,實現了輸入、輸出數據的傳輸。通過綜合實驗系統設計,使學生得到控制系統設計和實驗調試等綜合能力的訓練。A comprehensive experimental case of the automatic control system is presented,which is the design of the temperature control system based on LabVIEW and SCM.The hardware part of the experimental system is composed of the SCM,temperature sensor,D/A conversion module,voltage regulating module and electric oven.The interface circuit between the SCM and each module is designed.In the software part,LabVIEW software is used to realize the control algorithm,and the monitoring interface is designed to realize the functions of parameter setting,temperature data real-time monitoring,etc.The serial communication program between the SCM and LabVIEW software is designed to realize the transmission of input and output data.Through the design of this comprehensive experimental system,students can get the comprehensive ability training for the control system design,experiment debugging,etc.
上傳時間: 2022-03-27
上傳用戶:qdxqdxqdxqdx
為了提高超高頻RFID系統中閱讀器在低信噪比的情況下仍具有較高的識別能力,提出一種基于FPGA系統結合軟件無線電方法實現超高頻RFID射頻前端電路方案。超高頻射頻識別系統必須符合EPC Class 1generation 2標準,所設計的電路系統以Xilinx公司的XC6SLX16-2CSG324FPGA芯片為硬件基礎,將數字基帶調制解調和中頻濾波電路在FPGA系統中設計實現,重點闡述了射頻前端電路的設計結構、AD/DA轉換電路,以及數字濾波器的設計。實驗結果表明,所設計的超高頻RFID閱讀器簡化了前端電路系統結構,提升了穩定性,增強了抗干擾能力。該電路系統在信噪比較低的情況下,能夠較好地實現915MHz頻率的射頻接收和發送。In order to improve the reader UHF RFID system still has a higher ability to identify,in the case of low signal-to-noise ratio.The UHF RFID systems must comply with EPC Class 1 generation 2 standard.In this paper,the design of the circuit system based on Xilinx's XC6SLX16-2CSG324 FPGA chip,and presents UHF RFID RF front-end circuit with software radio based on FPGA system.Digital baseband modem and IF filter circuit is designed and implemented in the FPGA system,and focused on designing the structure of the RF front-end circuit,AD/DA conversion circuits,and digital filter.Experimental results show that the UHF RFID reader de...
標簽: 915mhz 超高頻 rfid 閱讀 射頻 前端 電路 設計
上傳時間: 2022-04-17
上傳用戶:shjgzh
#include "NUC1xx.h"#include "Hal.h"#include "pwm.h"//wait current PWM cycle done, otherwise there maybe short pulse on FETvoid PWM_Stop(U8 ch){ switch(ch) { case PWM_CHANNEL_A: PWMA->u32CNR1 = 0; PWMA->u32CMR1 = 0; while(PWMA->u32PDR1 != 0); break; case PWM_CHANNEL_B: PWMA->u32CNR2 = 0; PWMA->u32CMR2 = 0; while(PWMA->u32PDR2 != 0); break; case PWM_CHANNEL_C: PWMA->u32CNR3 = 0; PWMA->u32CMR3 = 0; while(PWMA->u32PDR3 != 0); break; default: while(1); } PWMA->u32POE &= ~(1<<ch); PWMA->u32PCR &= ~(1<<(ch*8));}
上傳時間: 2022-06-01
上傳用戶:kingwide