NAME: u2440mon.c DESC: u2440mon entry point,menu,download HISTORY: Mar.25.2002:purnnamu: S3C2400X profile.c is ported for S3C2410X. Mar.27.2002:purnnamu: DMA is enabled. Apr.01.2002:purnnamu: isDownloadReady flag is added. Apr.10.2002:purnnamu: - Selecting menu is available in the waiting LOOP. So, isDownloadReady flag gets not needed - UART ch.1 can be selected for the console. Aug.20.2002:purnnamu: revision number change 0.2 -> R1.1 Sep.03.2002:purnnamu: To remove the power noise in the USB signal, the unused CLKOUT0,1 is disabled.
標簽： 2440 mon download purnnamu
上傳時間： 2016-05-12
上傳用戶：wff
//*** *** *** *** *** *** *** *** *** *** *** *** *** * // MSP-FET430x110 Demo - Software Toggle P1.0 // // Description: Toggle P1.0 by xor ing P1.0 inside of a software LOOP. // ACLK = n/a, MCLK = SMCLK = default DCO ~800k // // MSP430F1121 // ----------------- // /|\| XIN|- // | | | // --|RST XOUT|- // | | // | P1.0|-->LED // // M. Buccini // Texas Instruments Inc. // Feb 2005 // Built with IAR Embedded Workbench Version: 3.21A
標簽： Software MSP-FET Toggle Demo
上傳時間： 2014-01-09
上傳用戶：問題問題
MediaPlayer代碼，部分代碼，合適請用： import java.awt.* import java.awt.event.* import javax.swing.* import javax.media.* import java.io.* import java.util.* //為了導入Vector //import com.sun.java.swing.plaf.windows.* public class MediaPlayer extends JFrame implements ActionListener,Runnable { private JMenuBar bar //菜單條 private JMenu fileMenu,choiceMenu,aboutMenu private JMenuItem openItem,openDirItem,closeItem,about,infor private JCheckBoxMenuItem onTop private boolean top=false,LOOP //設定窗口是否在最前面 private Player player //Play是個實現Controller的接口 private File file,listFile //利用File類結合JFileChooser進行文件打開操作,后則與list.ini有關
標簽： MediaPlayer 代碼
上傳時間： 2016-07-08
上傳用戶：爺的氣質
ADM6993F/FXFiber to Fast Ethernet Converter (TS1000 CPE Complied) The ADM6993F/FX is a single chip integrating two 10/100 Mbps MDIX TX/FX transceivers, a three-port 10/100M Ethernet L2 switch controller, and one OAM engine to meet demanding applications, including Fiber-to-Ethernet media converters, especially the fiber to the home (FTTH) media converters. The ADM6993F/FX feature set includes link pass through (LPT), TS1000 OAM frame receiving/processing/transmitting, programmable link status LED display, various LOOP-back modes, and one configurable MII ports for snooping/inserting OAM frame from/to 100Fx. The ADM6993FX is the environmentally friendly “green” package version.
標簽： 6993 ADM Converter Ethernet
上傳時間： 2014-01-01
上傳用戶：hebmuljb
This GLib version 2.16.1. GLib is the low-level core library that forms the basis for projects such as GTK+ and GNOME. It provides data structure handling for C, portability wrappers, and interfaces for such runtime functionality as an event LOOP, threads, dynamic loading, and an object system.
標簽： GLib the low-level projects
上傳時間： 2013-12-19
上傳用戶：tb_6877751
DDR SDRAM控制器的VHDL源代碼，含詳細設計文檔。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked LOOP (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上傳時間： 2014-11-01
上傳用戶：l254587896
A novel met hod t o p artially compensate sigma2delta shap ed noise is p rop osed. By injecting t he comp en2 sation cur rent int o t he p assive LOOP f ilte r during t he delay time of t he p hase f requency detect or ( PFD) , a maximum reduction of t he p hase noise by about 16dB can be achieved. Comp a red t o ot he r compensation met hods , t he tech2 nique p rop osed he re is relatively simple and easy t o implement . Key building blocks f or realizing t he noise cancel2 lation , including t he delay va riable PFD and comp ensation cur rent source , a re sp ecially designed. Bot h t he behavior level and circuit level simulation results a re p resented.
標簽： sigma2delta compensate injecting artially
上傳時間： 2013-12-18
上傳用戶：qlpqlq
This document describes how to switch to and program the unisersal serial bus (USB) analog phase-locked LOOP (APLL) on the C5506/C5507/C5509A devices. Example assembly programs for programming and switching to and from the APLL are also provided in the attached zip file. It is assumed that the reader is familiar with the use and operation of the C5506/C5507/C5509A USB digital phase-locked LOOP (DPLL) and C55x™ Digital Signal Processor (DSP) IDLE procedures.
標簽： describes unisersal document phase-lo
上傳時間： 2014-01-13
上傳用戶：hustfanenze
以傳統的C/SDK 撰寫Windows 程序，最大的好處是可以清楚看見整個程序的來龍去脈 和消息動向，然而這些重要的動線在MFC 應用程序中卻隱晦不明，因為它們被Application Framework 包起來了。這一章主要目的除了解釋MFC 應用程序的長像，也要從MFC 源代 碼中檢驗出一個Windows 程序原本該有的程序進入點（WinMain）、視窗類別注冊 （RegisterClass）、窗口產生（CreateWindow）、消息循環（Message LOOP）、窗口函數 （WindowProcedure）等等動作，抽絲剝繭徹底了解一個MFC 程序的誕生與結束，以及生 命過程。
上傳時間： 2017-03-22
上傳用戶：athjac
合眾達的DM642示例工程，包括視頻LOOP，spi接口，SD卡，i2c接口，FLASH自動boot
上傳時間： 2017-04-13
上傳用戶：jing911003
