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The field of digital communication has evolved rapidly in the past few
decades, with commercial applications proliferating in wireline communi-
cation networks (e.g., digital subscriber LOOP, cable, fiber optics), wireless
communication (e.g., cell phones and wireless local area networks), and stor-
age media (e.g., compact discs, hard drives). The typical undergraduate and
graduate student is drawn to the field because of these applications, but is
often intimidated by the mathematical background necessary to understand
communication theory.
標(biāo)簽：
Communication
Fundamentals
Digital
of
上傳時(shí)間：
2020-05-27
上傳用戶：shancjb
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Public telephone operators and new independent wireless operators through-
out the world are deploying wireless access in an effort to drastically reduce
delivery costs in the most expensive part of the network?the local LOOP.
Available radio technology enables both existing and new entrants to access
subscribers in a rapid manner and deliver their basic telephony products and
broadband-enhanced services.
標(biāo)簽：
Transmission
Handbooks
Systems
Design
上傳時(shí)間：
2020-06-01
上傳用戶：shancjb
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PLL(Phase Locked LOOP)： 為鎖相回路或鎖相環(huán)，用來統(tǒng)一整合時(shí)鐘信號(hào)，使高頻器件正常工作，如內(nèi)存的存取資料等。PLL用于振蕩器中的反饋技術(shù)。 許多電子設(shè)備要正常工作，通常需要外部的輸入信號(hào)與內(nèi)部的振蕩信號(hào)同步。一般的晶振由于工藝與成本原因，做不到很高的頻率，而在需要高頻應(yīng)用時(shí)，由相應(yīng)的器件VCO，實(shí)現(xiàn)轉(zhuǎn)成高頻，但并不穩(wěn)定，故利用鎖相環(huán)路就可以實(shí)現(xiàn)穩(wěn)定且高頻的時(shí)鐘信號(hào)。
標(biāo)簽：
PLL
鎖相環(huán)
上傳時(shí)間：
2021-07-23
上傳用戶：紫陽帝尊
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Wherever possible the overall technique used for this series will be "definition by example" withgeneric formulae included for use in other applications. To make stability analysis easy we will usemore than one tool from our toolbox with data sheet information, tricks, rules-of-thumb, SPICESimulation, and real-world testing all accelerating our design of stable operational amplifier (op amp)circuits. These tools are specifically targeted at voltage feedback op amps with unity-gain bandwidths<20 MHz, although many of the techniques are applicable to any voltage feedback op amp. 20 MHz ischosen because as we increase to higher bandwidth circuits there are other major factors in closing theLOOP: such as parasitic capacitances on PCBs, parasitic inductances in capacitors, parasitic inductancesand capacitances in resistors, etc. Most of the rules-of-thumb and techniques were developed not justfrom theory but from the actual building of real-world circuits with op amps <20 MHz.
標(biāo)簽：
運(yùn)算放大器
上傳時(shí)間：
2021-11-01
上傳用戶：
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ADC模數(shù)轉(zhuǎn)換器件Altium Designer AD原理圖庫元件庫SV text has been written to file : 4.4 - ADC模數(shù)轉(zhuǎn)換器件.csvLibrary Component Count : 29Name Description----------------------------------------------------------------------------------------------------ADC0800 National 8-Bit Analog to Digital ConverterADC0809 ADC0831 ADCADC0832 ADC8 Generic 8-Bit A/D ConverterCLC532 High-Speed 2:1 Analog MultiplexerCS5511 National 16-Bit Analog to Digital ConverterDAC8 Generic 8-Bit D/A ConverterEL1501 Differential line Driver/ReceiverEL2082 Current-Mode MultiplierEL4083 Current Mode Four Quadrant MultiplierEL4089 DC Restored Video AmplifierEL4094 Video Gain Control/FaderEL4095 Video Gain Contol/Fader/MultiplexerICL7106 LMC6953_NSC PCI Local Bus Power SupervisorMAX4147 300MHz, Low-Power, High-Output-Current, Differential Line DriverMAX4158 350MHz 2-Channel Video Multiplexer-AmplifierMAX4159 350MHz 2-Channel Video Multiplexer-AmplifierMAX4258 250MHz, 2-Channel Video Multiplexer-AmplifierMAX4259 250MHz 2-Channel Video Multiplexer-AmplifierMAX951 Ultra-Low-Power, Single-Supply Op Amp + Comparator + ReferenceMAX952 Ultra-Low-Power, Single-Supply Op Amp + Comparator + ReferenceMC1496 Balanced Modulator/DemodulatorPLL100k Generic Phase Locked LOOPPLL10k Generic Phase Locked LOOPPLL5k Generic Phase Locked LOOPPLLx Generic Phase Locked LOOP水位計(jì)
標(biāo)簽：
adc
模數(shù)轉(zhuǎn)換
altium designer
上傳時(shí)間：
2022-03-13
上傳用戶：
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HX711_1Kg#include "HX711.h"float Weight = 0;void setup(){ Init_Hx711(); //初始化HX711模塊連接的IO設(shè)置 Serial.begin(9600); Serial.print("Welcome to use!\n"); delay(3000); Get_Maopi(); //獲取毛皮}void LOOP(){ Weight = Get_Weight(); //計(jì)算放在傳感器上的重物重量 Serial.print(float(Weight/1000),3); //串口顯示重量 Serial.print(" kg\n"); //顯示單位 Serial.print("\n"); //顯示單位 delay(1000); //延時(shí)1s}
標(biāo)簽：
arduino
電子秤
上傳時(shí)間：
2022-03-20
上傳用戶：
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以STM32F103C8T6為核心,設(shè)計(jì)了無刷直流電機(jī)控制器硬件電路。電路主要包括IR2310構(gòu)成的PWM驅(qū)動(dòng)電路、IRF3808構(gòu)成的逆變電路、增量式旋轉(zhuǎn)編碼構(gòu)成的速度反饋電路。控制器具有CAN和RS232通信接口,可與計(jì)算機(jī)或PLC構(gòu)成速度或位置伺服系統(tǒng)。利用由xPC目標(biāo)搭建的半實(shí)物仿真平臺(tái)對(duì)PI參數(shù)進(jìn)行整定。測(cè)試了控制器的速度伺服響應(yīng)性能,給定速度為2400rpm時(shí),控制器響應(yīng)時(shí)間為0.32s。實(shí)驗(yàn)結(jié)果表明,系統(tǒng)工作可靠,穩(wěn)定性好,響應(yīng)速度快,可以滿足上肢康復(fù)機(jī)器人的機(jī)械臂速度控制性能要求。The hardware circuit of Brushless DC motor controller is designed by taking STM32F103C8T6 as the core,which mainly includes PWM driving circuits made up of IR2310,inverter circuit formed by IRF3808,speed feedback circuit composed of incremental rotary encoder and so on.Speed servo control system or position servo control system can be composed of BLDM controller with computer or PLC through CAN communication interface or RS232 serial communication interface.By using the hardware in the LOOP simulation platform built by xPC target,the PI parameters are set up.The Speed servo response performance of the controller is tested.When the speed is 2 400 rpm,the response time of the controller is 0...
標(biāo)簽：
stm32
無刷直流電機(jī)
上傳時(shí)間：
2022-05-07
上傳用戶：
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Abstract: A sliding mode observer and fractional-order phase-locked LOOP (FO-PLL) method is proposed for the sensorless speed control of a permanent magnet synchronous motor (PMSM).The saturation function is adopted in order to reduce the chattering phenomenon caused by the sliding mode observer. In this proposed FO-PLL, method, a regulable fractional order r is involved, which means that the FO-PLL provides an extra degree of freedom. In fact, the conventional phase-locked LOOP (PLL) applied in sensorless PMSM control can be seen as a special case of the proposed FO-PLL. By selecting a proper fractional order r a better performance may be achieved. The computer simulation results demonstrate the effectiveness of the proposed method.Key words: fractional calculus; fractional order phase-locked LOOP; sensorless control; sliding mode observer; permanent magnet synchronous motor; speed controll
標(biāo)簽：
滑模觀測(cè)器
傳感器
pmsm
矢量控制
上傳時(shí)間：
2022-06-18
上傳用戶：
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一.基礎(chǔ)理論鎖相環(huán)路（Phase Locked LOOP）是一個(gè)閉環(huán)的相位控制系統(tǒng)，它的輸出信號(hào)的相位能自動(dòng)跟蹤輸入信號(hào)相位。系統(tǒng)框圖如下：當(dāng)0，（1）與0：（1）相等時(shí)，兩矢量以相同的角速度旋轉(zhuǎn)，相對(duì)位置，即夾角維持不變，通常數(shù)值又較小，這就是環(huán)路的鎖定狀態(tài)。從輸入信號(hào)加到鎖相環(huán)路的輸入端開始，一直到環(huán)路達(dá)到鎖定的全過程，稱為捕獲過程。設(shè)系統(tǒng)最初進(jìn)入同步狀態(tài)[2nrtto，e，.]的時(shí)間為1。。那么從1=1，的起始狀態(tài)到達(dá)進(jìn)入同步狀態(tài)的全部過程就稱為鎖相環(huán)路的捕獲過程。捕獲過程所需的時(shí)間T，=1，-1，稱為捕獲時(shí)間。顯然，捕獲時(shí)間T，的大小不但與環(huán)路的參數(shù)有關(guān)，而且與起始狀態(tài)有關(guān)。對(duì)一定的環(huán)路來說，是否能通過捕獲而進(jìn)入同步完全取決于起始頻差8.（4）-Ao。。若Ao，超過某一范圍，環(huán)路就不能捕獲了。這個(gè)范圍的大小是鎖相環(huán)路的一個(gè)重要性能指標(biāo)，稱為環(huán)路的捕獲帶Ao，。
標(biāo)簽：
射頻鎖相環(huán)
上傳時(shí)間：
2022-06-21
上傳用戶：
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Agenda■Motor Types Overview■BLDC Motor Applications■Comparison of DC to Brushless DC Motors■Hall Sensors■Six-Step Commutation■Sensorless Commutation with Back-EMFVector Motor Control basicsClosed-LOOP Speed Control■Introduction to BLDC Motor Control Evaluation Kit■SummaryAll the popular motor types have their specific applications, and all can be controlled with microcontrollers.We wll talk about Brushless DC motors as it is the fast growing motor type today.Motors used in modern Air conditioners, home appliances, tools, even electric bikes are all going to Brushless DC.
標(biāo)簽：
bldc
電機(jī)驅(qū)動(dòng)
上傳時(shí)間：
2022-07-07
上傳用戶：
