This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ microprocessor.
上傳時間： 2013-10-15
上傳用戶：euroford
This application note covers the design considerations of a system using the performance features of the LogiCORE™ IP Advanced eXtensible Interface (AXI) Interconnect core. The design focuses on high system throughput through the AXI Interconnect core with F MAX and area optimizations in certain portions of the design. The design uses five AXI video direct memory access (VDMA) engines to simultaneously move 10 streams (five transmit video streams and five receive video streams), each in 1920 x 1080p format, 60 Hz refresh rate, and up to 32 data bits per pixel. Each VDMA is driven from a video test pattern generator (TPG) with a video timing controller (VTC) block to set up the necessary video timing signals. Data read by each AXI VDMA is sent to a common on-screen display (OSD) core capable of multiplexing or overlaying multiple video streams to a single output video stream. The output of the OSD core drives the DVI video display interface on the board. Performance monitor blocks are added to capture performance data. All 10 video streams moved by the AXI VDMA blocks are buffered through a shared DDR3 SDRAM memory and are controlled by a MicroBlaze™ processor. The reference system is targeted for the Virtex-6 XC6VLX240TFF1156-1 FPGA on the Xilinx® ML605 Rev D evaluation board
標(biāo)簽： XAPP 740 AXI 互聯(lián)
上傳時間： 2013-11-14
上傳用戶：fdmpy
Xilinx is disclosing this user guide, manual, release note, and/or specification (the “Documentation”) to you solely for use in the development of designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit the Documentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reserves the right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errors contained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information.
標(biāo)簽： CPLD
上傳時間： 2013-10-22
上傳用戶：李哈哈哈
This application note describes a reference system which illustrates how to build an embeddedPowerPC® system using the Xilinx 1-Gigabit Ethernet Media Access Controller processor core.This system has the PLB_Gemac configured to use Scatter/Gather Direct Memory Access andthe Serializer/Deserializer (SerDes) interface. This application note describes how to set up thespecific clocking structure required for the SerDes interface and the constraints to be added tothe UCF file. This reference system is complete with a standalone software application to testsome of the main features of this core, including access to registers, DMA capabilities, transmitand receive in loopback mode. This reference system is targeted for the ML300 evaluationboard.
上傳時間： 2013-11-01
上傳用戶：truth12
The Tri-Mode Ethernet MAC (TEMAC) UltraController-II module is a minimal footprint,embedded network processing engine based on the PowerPC™ 405 (PPC405) processor coreand the TEMAC core embedded within a Virtex™-4 FX Platform FPGA. The TEMACUltraController-II module connects to an external PHY through Gigabit Media IndependentInterface (GMII) and Management Data Input/Output (MDIO) interfaces and supports tri-mode(10/100/1000 Mb/s) Ethernet. Software running from the processor cache reads and writesthrough an On-Chip Memory (OCM) interface to two FIFOs that act as buffers between thedifferent clock domains of the PPC405 OCM and the TEMAC.
上傳時間： 2013-10-26
上傳用戶：yuzsu
在現(xiàn)代通信系統(tǒng)中，電話語音的頻帶被限制在300 Hz～4 kHz的范圍內(nèi)，帶來了語音可懂度和自然度的降低。為了在不增加額外成本的前提下提高語音的可懂度和自然度，進行了電話語音頻帶擴展的研究。提出了一種改進的基于碼本映射的語音帶寬擴展算法：在碼本映射的過程中，使用加權(quán)系數(shù)來得到映射碼本。客觀測試結(jié)果表明，用此算法得到的寬帶語音的譜失真度比用一般的碼本映射降低至少2%。主觀測試結(jié)果表明，用此算法得到的寬帶語音具有更好的可懂度和自然度。 Abstract: In modern communication systems， the bandwidth of telephone speech is limited from 300Hz to 4 kHz， which reduces the intelligibility and naturalness of speech. Telephone speech bandwidth extension is researched to get wideband speech and to improve its intelligibility and naturalness， without increasing extra costs. This paper put forward an improved algorithm of speech bandwidth extension based on codebook mapping. In the process of codebook mapping， weighted coefficients were used to get mapping codebook. Objective tests show that spectral distortion of wideband speech obtained by this algorithm reduces at least 2%， comparing to conditional codebook mapping. Subjective tests show that the wideband speech obtained by this algorithm has better intelligibility and naturalness.
上傳時間： 2014-12-29
上傳用戶：15501536189
特點 最高輸入頻率 10KHz 顯示范圍0-9999（一段設(shè)定）0至999999累積量 計數(shù)速度 50/10000脈波/秒可選擇 輸入脈波具有預(yù)設(shè)刻度功能 累積量同步（批量）或非同步（批次）計數(shù)可選擇 數(shù)位化指撥設(shè)定操作簡易 計數(shù)暫時停止功能 1組報警功能 2:主要規(guī)格 脈波輸入型式: Jump-pin selectable current sourcing(NPN) or current sinking (PNP) 脈波觸發(fā)電位: HI bias (CMOS) (VIH=7.5V, VIL=5.5V) LO bias (TTL) (VIH=3.7V, VIL=2.0V) 最高輸入頻率: <10KHz (up,down,up/down mode) 輸出動作時間 : 0.1 to 99.9 second adjustable 輸出復(fù)歸方式: Manual(N) or automatic (R or C) can be modif 繼電器容量: AC 250V-5A, DC 30V-7A 顯示值范圍: 0-9999（PV,SV） 0-999999(TV) 顯示幕: Red high efficiency LEDs high 7.0mm (.276")(PV,SV) Red high efficiency LEDs high 9.2mm (.36")(TV) 參數(shù)設(shè)定方式: Touch switches 感應(yīng)器電源: 12VDC +/-3%(<60mA) 記憶方式: Non-volatile E2PROM memory 絕緣耐壓能力: 2KVac/1 min. (input/output/power) 1600Vdc (input/output) 使用環(huán)境條件: 0-50℃(20 to 90% RH non-condensed) 存放環(huán)境條件: 0-70℃(20 to 90% RH non-condensed) CE認(rèn)證: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
標(biāo)簽： 設(shè)定 累積計數(shù)器
上傳時間： 2013-10-24
上傳用戶：wvbxj
特點 顯示值范圍-199999至999999位數(shù) 最高輸入頻率 5KHz 90度相位差加減算具有提高解析度4倍功能 輸入脈波具有預(yù)設(shè)刻度功能 定位基準(zhǔn)值可任意設(shè)定 比較磁滯值可任意設(shè)定 數(shù)位化指撥設(shè)定操作簡易 3組繼電器輸出功能 2:主要規(guī)格 脈波輸入型式: Jump-pin selectable current sourcing(NPN) or current sinking (PNP) 脈波觸發(fā)電位: HI bias (CMOS) (VIH=7.5V, VIL=5.5V) LO bias (TTL) (VIH=3.7V, VIL=2.0V) 最高輸入頻率: <5KHz 定位置范圍: -199999 to 999999 second adjustabl 比較磁滯范圍: 0 to 9999 adjustable 繼電器容量: AC 250V-5A, DC 30V-7A 顯示值范圍: -199999 to 999999 顯示幕: Red high efficiency LEDs high 9.2mm (.36") 參數(shù)設(shè)定方式: Touch switches 感應(yīng)器電源: 12VDC +/-3%(<60mA) 記憶方式: Non-volatile E2PROM memory 絕緣耐壓能力: 2KVac/1 min. (input/output/power) 1600Vdc (input/output) 使用環(huán)境條件: 0-50℃(20 to 90% RH non-condensed) 存放環(huán)境條件: 0-70℃(20 to 90% RH non-condensed) CE認(rèn)證: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
上傳時間： 2014-12-03
上傳用戶：xjz632
特點 精確度0.25%滿刻度 ±1位數(shù) 輸入配線系統(tǒng)可任意選擇 CT比可任意設(shè)定 具有異常電流值與異常次數(shù)記錄保留功能 電流過高或過低檢測可任意設(shè)定 報警繼電器復(fù)歸方式可任意設(shè)定 尺寸小,穩(wěn)定性高 2.主要規(guī)格 輔助電源: AC110V&220V ±20%(50 or 60Hz) AC220V&440V ±20%(50 or 60Hz)(optional) 精確度: 0.25% F.S. ±1 digit 輸入負(fù)載: <0.2VA (Current) 最大過載能力 : Current related input: 2 x rated continuous 10 x rated 30 sec. 25 x rated 3sec. 50 x rated 1 sec. 輸入電流范圍: AC0-5A (10-1000Hz) CT ratio : 1-2000 adjustable 啟動延遲動作時間: 0-99.9 second adjustable 繼電器延遲動作時間: 0-99.9 second adjustable 繼電器復(fù)歸方式: Manual (N) / latch(L) can be modified 繼電器磁滯范圍: 0-999 digit adjustable 繼電器動作方向: HI /LO/GO/HL can be modified 繼電器容量: AC 250V-5A, DC 30V-7A 過載顯示: "doFL" 溫度系數(shù): 50ppm/℃ (0-50℃) 顯示幕: Red high efficiency LEDs high 14.22mm(.56")(PV) Red high efficiency LEDs high 14.22mm(.276")(NO) 參數(shù)設(shè)定方式: Touch switches 記憶型式 : Non-volatile E2PROM memory 絕緣耐壓能力: 2KVac/1 min. (input/output/power) 1600Vdc(input/output 使用環(huán)境條件 : 0-50℃(20 to 90% RH non-condensed) 存放環(huán)境條件: 0-70℃(20 to 90% RH non-condensed) CE認(rèn)證: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
上傳時間： 2013-10-14
上傳用戶：wanghui2438
特點 精確度0.1%滿刻度 ±1位數(shù) 可量測 交直流電流/交直流電壓/電位計/傳送器/Pt-100/荷重元/電阻 等信號 顯示范圍-1999-9999可任意規(guī)劃 具有異常值與異常次數(shù)記錄保留功能 異常信號過高或過低或范圍內(nèi)或范圍外檢測可任意設(shè)定 報警繼電器復(fù)歸方式可任意設(shè)定 尺寸小,穩(wěn)定性高 2.主要規(guī)格 精確度: 0.1% F.S. ±1 digit 0.2% F.S. ±1 digit(AC) 取樣時間: 16 cycles/sec. 顯示值范圍: -1999 - +9999 digit adjustable 啟動延遲動作時間: 0-99.9 second adjustable 繼電器延遲動作時間: 0-99.9 second adjustable 繼電器復(fù)歸方式: Manual (N) / latch(L) can be modified 繼電器動作方向: HI /LO/GO/HL can be modified 繼電器容量: AC 250V-5A, DC 30V-7A 過載顯示: "doFL" 溫度系數(shù): 50ppm/℃ (0-50℃) 顯示幕: Red high efficiency LEDs high 14.22mm(.56")(PV) Red high efficiency LEDs high 7.0mm(.276")(NO) 參數(shù)設(shè)定方式: Touch switches 記憶型式 : Non-volatile E2PROM memory 絕緣耐壓能力: 2KVac/1 min. (input/output/power) 1600Vdc(input/output 使用環(huán)境條件 : 0-50℃(20 to 90% RH non-condensed) 存放環(huán)境條件: 0-70℃(20 to 90% RH non-condensed) CE認(rèn)證: EN 55022:1998/A1:2000 Class A EN 61000-3-2:2000 EN 61000-3-3:1995/A1:2001 EN 55024:1998/A1:2001
上傳時間： 2013-11-02
上傳用戶：fandeshun
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