基于OFDM的無線寬帶系統仿真It contains mainly two parts, i.e. Link-level simulator and system-level simulator. Link-level simulator focus on a single-cell single-user scenario, where signal is transmitted from tx, and estimated at rx. Comparing the difference in tx/rx signal, the error rate can be found out. The output of the Link-level simulator is the BLER/BER vs. SNR mapping table, that can be used for the system-level simulation. System-level simulator focus on a multi-cell multi-user scenario. For the sake of simplicity, it takes the mapping table aquired in the Link-level simulation, measure the actural SNR, and finds the corresponding error rate.
標簽： simulator i.e. system-level Link-level
上傳時間： 2016-03-15
上傳用戶：xsnjzljj
In this first part of the book the Vienna Link Level (LL) Simulators are described. The first chapter provides basics of LL simulations, introduces the most common variables and parameters as well as the transceiver structures that are applied in Long-Term Evolution (LTE) and Long-Term Evolution-Advanced (LTEA). We focus here mostly on the Downlink (DL) of LTE as most results reported in later chapters are related to DL transmissions.
標簽： LTE-Advanced Simulators Vienna
上傳時間： 2020-06-01
上傳用戶：shancjb
Link & System-Level Wireless OFDM System Simulator Version，仿真了OFDM
標簽： System-Level Simulator Wireless Version
上傳時間： 2013-12-18
上傳用戶：xg262122
J-Link用戶手冊(中文)，是學習ARM開發的好東知。
上傳時間： 2013-04-24
上傳用戶：mingaili888
·摘要： 針對DSP芯片TS201的LINK口互連在高速數據通信中存在數據錯誤、突發數據塊傳輸不穩定等缺點,在分析其通信協議的基礎上,并結合實際應用,提出了設計LINK口通信的關鍵要求,給出設計的要點,設計與實現了TS201的LINK 121互連以及FPGA(Xilinx公司的XC4VFX60)與TS201 LINK口互連,得到了實際測試結果;結果表明,所設計的LINK口互連具備的優點有
上傳時間： 2013-06-08
上傳用戶：417313137
ST-Link仿真器驅動程序(IAR EWARM V5升級版)
上傳時間： 2013-04-24
上傳用戶：hewenzhi
J-LINK驅動程序arm v4.10b，需要的下載用用吧。
上傳時間： 2013-04-24
上傳用戶：chfanjiang
FPGA-based link layer chip S19202 configuration
標簽： configuration FPGA-based S19202 layer
上傳時間： 2013-08-18
上傳用戶：xsnjzljj
DC-link Automotive: MKP1849 (Customized)電動汽車電驅直流母線電容（顧客訂制品）MKP1849系列.MKP1849-可集成母線排，大大降低了寄生電感，提高了系統穩定性。
上傳時間： 2013-10-13
上傳用戶：nanfeicui
The PCA9517 is a CMOS integrated circuit that provides level shifting between lowvoltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Usingthe PCA9517 enables the system designer to isolate two halves of a bus for both voltageand capacitance. The SDA and SCL pins are over voltage tolerant and arehigh-impedance when the PCA9517 is unpowered.
標簽： translating Level 9517 PCA
上傳時間： 2013-12-25
上傳用戶：wsf950131
