NAME: u2440mon.c
DESC: u2440mon entry point,menu,download
HISTORY:
Mar.25.2002:purnnamu: S3C2400X profile.c is ported for S3C2410X.
Mar.27.2002:purnnamu: DMA is enabled.
Apr.01.2002:purnnamu: isDownloadReady flag is added.
Apr.10.2002:purnnamu: - Selecting menu is available in the waiting Loop.
So, isDownloadReady flag gets not needed
- UART ch.1 can be selected for the console.
Aug.20.2002:purnnamu: revision number change 0.2 -> R1.1
Sep.03.2002:purnnamu: To remove the power noise in the USB signal, the unused CLKOUT0,1 is disabled.
ADM6993F/FXFiber to Fast Ethernet Converter (TS1000 CPE Complied)
The ADM6993F/FX is a single chip integrating two 10/100 Mbps MDIX TX/FX transceivers, a three-port 10/100M Ethernet L2 switch controller, and one OAM engine to meet demanding applications, including Fiber-to-Ethernet media converters, especially the fiber to the home (FTTH) media converters. The ADM6993F/FX feature set includes link pass through (LPT), TS1000 OAM frame receiving/processing/transmitting, programmable link status LED display, various Loop-back modes, and one configurable MII ports for snooping/inserting OAM frame from/to 100Fx. The ADM6993FX is the environmentally friendly “green” package version.
This GLib version 2.16.1. GLib is the low-level core
library that forms the basis for projects such as GTK+ and GNOME. It
provides data structure handling for C, portability wrappers, and
interfaces for such runtime functionality as an event Loop, threads,
dynamic loading, and an object system.
DDR SDRAM控制器的VHDL源代碼，含詳細設(shè)計文檔。
The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect
choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock
Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS),
and Digital Frequency Synthesis (DFS) functions. This application note describes a controller
design for a 16-bit DDR SDRAM. The application note and reference design are enhanced
versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz,
16-bit data changes at both clock edges. The reference design is fully synthesizable and
achieves 133 MHz performance with automatic place and route tools.
A novel met hod t o p artially compensate sigma2delta shap ed noise is p rop osed. By injecting t he comp en2
sation cur rent int o t he p assive Loop f ilte r during t he delay time of t he p hase f requency detect or ( PFD) , a maximum
reduction of t he p hase noise by about 16dB can be achieved. Comp a red t o ot he r compensation met hods , t he tech2
nique p rop osed he re is relatively simple and easy t o implement . Key building blocks f or realizing t he noise cancel2
lation , including t he delay va riable PFD and comp ensation cur rent source , a re sp ecially designed. Bot h t he behavior
level and circuit level simulation results a re p resented.
This document describes how to switch to and program the unisersal serial bus (USB)
analog phase-locked Loop (APLL) on the C5506/C5507/C5509A devices. Example
assembly programs for programming and switching to and from the APLL are also
provided in the attached zip file. It is assumed that the reader is familiar with the use
and operation of the C5506/C5507/C5509A USB digital phase-locked Loop (DPLL) and
C55x™ Digital Signal Processor (DSP) IDLE procedures.
