This manual describes Freescale’s IEEE™ 802.15.4 Standard compliant MAC/PHY software. The Freescale 802.15.4 MAC/PHY software is designed for use with the Freescale MC1319x and MC1320x, family of short range, low power, 2.4 GHz Industrial, Scientific, and Medical (ISM) band transceivers, designed for use with the HCS08 Family of MCUs. The MAC/PHY software also works with the MC1321x family of short range, low power, 2.4 GHz ISM band transceivers that incorporate a low power 2.4 GHz radio frequency transceiver and an 8-bit microcontroller into a single LGA package. Throughout this manual, the term transceiver refers to either the MC1319x, MC1320x, or the internal counterpart inside the MC1321x System in a Package (SiP).
標簽： Freescale describes compliant Standard
上傳時間： 2016-04-17
上傳用戶：caiiicc
/* * The internal form of a hash table. * * The table is an array indexed by the hash of the key collisions * are resolved by hanging a linked list of hash entries off each * element of the array. Although this is a really simple design it * isn t too bad given that pools have a low allocation overhead. */ split from apache for general usage
上傳時間： 2014-01-07
上傳用戶：gtf1207
1、提取原蛋白質相互作用網絡的所有節點 2、分別計算原蛋白質相互作用網絡每個節點的度 3、從所有節點中選擇具有最高度的節點，反復的添加邊，直到它的度值等于原蛋白質相互作用網絡該節點的度值 4、在為節點添加邊時，從剩余節點中選擇節點的方法是其度分布近似服從power-low分布 5、令t的值為零，則每個節點被選到的可能性都是相同的，由于在原蛋白質相互作用網絡存在大量的低度節點，所以集散節點會優先連接低度節點。 這樣創建的網絡就為負相關蛋白質互作網絡
上傳時間： 2014-01-13
上傳用戶：skfreeman
the geometry of a diffraction grating, a common illustration in textbooks of optics, spectroscopy, and analytical chemistry. Sliders on the figures allow real-time interactive control of the incidence angle, grating ruling density (lines/mm), wavelength, and diffraction order.
標簽： illustration spectroscopy diffraction textbooks
上傳時間： 2016-06-04
上傳用戶：極客
用fpga實現的DA轉換器，有說明和源碼，VDHL文件。 A PLD Based Delta-Sigma DAC Delta-Sigma modulation is the simple, yet powerful, technique responsible for the extraordinary performance and low cost of today s audio CD players. The simplest Delta-Sigma DAC consists of a Delta-Sigma modulator and a one bit DAC. Since, both of these components can be realized using digital circuits, it is possible to implement a low precision Delta-Sigma DAC using a PLD.
上傳時間： 2016-06-10
上傳用戶：bjgaofei
DESCRIPTION : BIN to seven segments converter -- segment encoding -- a -- +---+ -- f | | b -- +---+ <- g -- e | | c -- +---+ -- d -- Enable (EN) active : high -- Outputs (data_out) active : low
標簽： DESCRIPTION converter segments encoding
上傳時間： 2016-08-17
上傳用戶：ainimao
ClustanGraphics聚類分析工具。提供了11種聚類算法。 Single Linkage (or Minimum Method, Nearest Neighbor) Complete Linkage (or Maximum Method, Furthest Neighbor) Average Linkage (UPGMA) Weighted Average Linkage (WPGMA) Mean Proximity Centroid (UPGMC) Median (WPGMC) Increase in Sum of Squares (Ward s Method) Sum of Squares Flexible (ß space distortion parameter) Density (or k-linkage, density-seeking mode analysis)
標簽： ClustanGraphics Complete Neighbor Linkage
上傳時間： 2014-01-02
上傳用戶：003030
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上傳時間： 2013-12-13
上傳用戶：himbly
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上傳時間： 2014-01-20
上傳用戶：三人用菜
This toolbox contains re-implementations of four different multi-instance learners, i.e. Diverse Density, Citation-kNN, Iterated-discrim APR, and EM-DD. Ensembles of these single multi-instance learners can be built with this toolbox
標簽： i.e. re-implementations multi-instance different
上傳時間： 2013-12-19
上傳用戶：haohaoxuexi
