LLCR Pin Socket Testing with the Model 3732 High Density Matrix Card Computer processors (CPUs) today have come a long way from the computer processors of the past. They draw more power, run at lower voltages, and have more pins than ever before.
上傳時間： 2013-10-24
上傳用戶：whenfly
根據看門狗電路的原理，設計出簡單適用、性能可靠的1TrL型看門狗電路以及價格低廉、性能可靠的微功耗CMOS型看門狗電路，同時還介紹了常用的uP監視器O型看門狗電路。關鍵詞：看門狗電路；1TrL型；CMOS型Abstract：In accordance with the principle of WDT (Watch Dog Timer 1circuit，design a，IT．L type WTD circuit，it is a dimple an d applicable an d reliable on performanceo Design a CMOS type WTD circuit，it is low prices and mini-power consumption。Also the article describes a common uP type WTD circuit。Key word：WDT circuit；TFL type；CMOS typ e
上傳時間： 2013-11-05
上傳用戶：685
The LPC1769/68/67/66/65/64 are ARM Cortex-M3 based microcontrollers for embedded applications featuring a high level of integration and low power consumption. The ARM Cortex-M3 is a next generation core that offers system enhancements such as enhanced debug features and a higher level of support block integration.
上傳時間： 2014-02-20
上傳用戶：13215175592
Virtex-5, Spartan-DSP FPGAs Application Note This application note demonstrates how efficient implementations of Digital Up Converters(DUC) and Digital Down Converters (DDC) can be done by leveraging the Xilinx DSP IPportfolio for increased productivity and reduced time to development. Step-by-step instruction is given on how to perform system-level trade off analysis and develop the most efficient FPGA implementation, thus allowing engineers a flexible, low-cost and low-power alternative to ASSP technologies.
標簽： Spartan-DSP Virtex FPGAs Ap
上傳時間： 2013-10-23
上傳用戶：raron1989
The CAT28LV64 is a low voltage, low power, CMOS Parallel EEPROM organized as 8K x 8−bits. It requires a simple interface for in−system programming. On−chip address and data latches, self−timed write cycle with auto−clear and VCC power up/down write protection eliminate additional timing and protection hardware. DATA Polling and Toggle status bit signal the start and end of the self−timed write cycle. Additionally, the CAT28LV64 features hardware and software write protection.
上傳時間： 2013-11-16
上傳用戶：浩子GG
MC9S08QG8英文資料 The MC9S08QG8 is the newest member of the Freescale 8-bit family of highly integratedmicrocontrollers, based on the high-performance yet low power HCS08 core. The MC9S08QG8is an excellent solution for power-sensitive applications with extended battery life and maximum performance down to 1.8VDC.
上傳時間： 2014-12-28
上傳用戶：dxxx
1、 支持USB 1.1通訊協議；2、 支持高速（Full Speed、12Mbps ）和低速（Low Speed、1.5Mbps ）傳輸；3、 6MHz晶體，鎖相環PLL振蕩器提供高速、低速所需時鐘源；4、 支持3個端口（endpoint），可獨立編程為IN 或 OUT端口。5、 PS/2：支持PS/2協議（eg.鼠標），與USB復用。
上傳時間： 2013-11-03
上傳用戶：hbsunhui
The PCA9534 is a 16-pin CMOS device that provide 8 bits of General Purpose parallel Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvements include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O configuration, 400 kHz clock frequency, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.
上傳時間： 2013-10-10
上傳用戶：inwins
The PCA9517 is a CMOS integrated circuit that provides level shifting between lowvoltage (down to 0.9 V) and higher voltage (2.7 V to 5.5 V) I2C-bus or SMBus applications.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling two buses of 400 pF. Usingthe PCA9517 enables the system designer to isolate two halves of a bus for both voltageand capacitance. The SDA and SCL pins are over voltage tolerant and arehigh-impedance when the PCA9517 is unpowered.
標簽： translating Level 9517 PCA
上傳時間： 2013-12-25
上傳用戶：wsf950131
The PCA9519 is a 4-channel level translating I2C-bus/SMBus repeater that enables theprocessor low voltage 2-wire serial bus to interface with standard I2C-bus or SMBus I/O.While retaining all the operating modes and features of the I2C-bus system during thelevel shifts, it also permits extension of the I2C-bus by providing bidirectional buffering forboth the data (SDA) and the clock (SCL) lines, thus enabling the I2C-bus or SMBusmaximum capacitance of 400 pF on the higher voltage side. The SDA and SCL pins areover-voltage tolerant and are high-impedance when the PCA9519 is unpowered.
標簽： 4channel transla level 9519
上傳時間： 2013-11-19
上傳用戶：jisiwole
