The PCA9544A provides 4 interrupt inputs, one for each channeland one open drain interrupt output. When an interrupt is generated byany device, it will be detected by the PCA9544A and the interruptoutput will be driven LOW. The channel need not be active fordetection of the interrupt. A bit is also set in the control byte.Bits 4 – 7 of the control byte correspond to channels 0 – 3 of thePCA9544A, respectively. Therefore, if an interrupt is generated byany device connected to channel 2, the state of the interrupt inputs isloaded into the control register when a read is accomplished.Likewise, an interrupt on any device connected to channel 0 wouldcause bit 4 of the control register to be set on the read. The mastercan then address the PCA9544A and read the contents of thecontrol byte to determine which channel contains the devicegenerating the interrupt. The master can then reconfigure thePCA9544A to select this channel, and locate the device generatingthe interrupt and clear it. The interrupt clears when the deviceoriginating the interrupt clears.
標(biāo)簽： 4channel multiple 9544A 9544
上傳時(shí)間： 2014-12-28
上傳用戶(hù)：潛水的三貢
The PCA9549 provides eight bits of high speed TTL-compatible bus switching controlledby the I2C-bus. The low ON-state resistance of the switch allows connections to be madewith minimal propagation delay. Any individual A to B channel or combination of channelscan be selected via the I2C-bus, determined by the contents of the programmable Controlregister. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow fromPort A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open,creating a high-impedance state between the two ports, which stops the data flow.An active LOW reset input (RESET) allows the PCA9549 to recover from a situationwhere the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-busstate machine and causes all the bits to be open, as does the internal power-on resetfunction.
標(biāo)簽： switch Octal 9549 with
上傳時(shí)間： 2014-11-22
上傳用戶(hù)：xcy122677
The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallelInput/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed toenhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvementsinclude higher drive capability, 5 V I/O tolerance, lower supply current, individual I/Oconfiguration, and smaller packaging. I/O expanders provide a simple solution whenadditional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc.The PCA9555 consists of two 8-bit Configuration (Input or Output selection); Input, Outputand Polarity Inversion (active HIGH or active LOW operation) registers. The systemmaster can enable the I/Os as either inputs or outputs by writing to the I/O configurationbits. The data for each Input or Output is kept in the corresponding Input or Outputregister. The polarity of the read register can be inverted with the Polarity Inversionregister. All registers can be read by the system master. Although pin-to-pin and I2C-busaddress compatible with the PCF8575, software changes are required due to theenhancements, and are discussed in Application Note AN469.
上傳時(shí)間： 2013-11-13
上傳用戶(hù)：fredguo
The PCA9548A is an octal bidirectional translating switch controlled via the I2C-bus. TheSCL/SDA upstream pair fans out to eight downstream pairs, or channels. Any individualSCx/SDx channel or combination of channels can be selected, determined by thecontents of the programmable control register.An active LOW reset input allows the PCA9548A to recover from a situation where one ofthe downstream I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets theI2C-bus state machine and causes all the channels to be deselected as does the internalPower-on reset function.
標(biāo)簽： channel 9548A 9548 PCA
上傳時(shí)間： 2013-10-13
上傳用戶(hù)：bakdesec
The PCA9557 is a silicon CMOS circuit which provides parallel input/output expansion for SMBus and I2C-bus applications. The PCA9557 consists of an 8-bit input port register, 8-bit output port register, and an I2C-bus/SMBus interface. It has low current consumption and a high-impedance open-drain output pin, IO0. The system master can enable the PCA9557’s I/O as either input or output by writing to the configuration register. The system master can also invert the PCA9557 inputs by writing to the active HIGH polarity inversion register. Finally, the system master can reset the PCA9557 in the event of a time-out by asserting a LOW in the reset input. The power-on reset puts the registers in their default state and initializes the I2C-bus/SMBus state machine. The RESET pin causes the same reset/initialization to occur without de-powering the part.
標(biāo)簽： C-bus SMBus reset port
上傳時(shí)間： 2014-01-18
上傳用戶(hù)：bs2005
SPCE061A單片機(jī)硬件結(jié)構(gòu) 從第一章中SPCE061A的結(jié)構(gòu)圖可以看出SPCE061A的結(jié)構(gòu)比較簡(jiǎn)單，在芯片內(nèi)部集成了ICE仿真電路接口、FLASH程序存儲(chǔ)器、SRAM數(shù)據(jù)存儲(chǔ)器、通用IO端口、定時(shí)器計(jì)數(shù)器、中斷控制、CPU時(shí)鐘、模-數(shù)轉(zhuǎn)換器AD、DAC輸出、通用異步串行輸入輸出接口、串行輸入輸出接口、低電壓監(jiān)測(cè)低電壓復(fù)位等若干部分。各個(gè)部分之間存在著直接或間接的聯(lián)系，在本章中我們將詳細(xì)的介紹每個(gè)部分結(jié)構(gòu)及應(yīng)用。2.1 μ’nSP™的內(nèi)核結(jié)構(gòu)μ’nSP™的內(nèi)核如0所示其結(jié)構(gòu)。它由總線、算術(shù)邏輯運(yùn)算單元、寄存器組、中斷系統(tǒng)及堆棧等部分組成，右邊文字為各部分簡(jiǎn)要說(shuō)明。算術(shù)邏輯運(yùn)算單元ALUμ’nSP™的ALU在運(yùn)算能力上很有特色，它不僅能做16位基本的算術(shù)邏輯運(yùn)算，也能做帶移位操作的16位算術(shù)邏輯運(yùn)算，同時(shí)還能做用于數(shù)字信號(hào)處理的16位×16位的乘法運(yùn)算和內(nèi)積運(yùn)算。1． 16位算術(shù)邏輯運(yùn)算不失一般性，μ’nSP™與大多數(shù)CPU類(lèi)似，提供了基本的算術(shù)運(yùn)算與邏輯操作指令，加、減、比較、取補(bǔ)、異或、或、與、測(cè)試、寫(xiě)入、讀出等16位算術(shù)邏輯運(yùn)算及數(shù)據(jù)傳送操作。2． 帶移位操作的16位算邏運(yùn)算對(duì)圖2.1稍加留意，就會(huì)發(fā)現(xiàn)μ’nSP™的ALU前面串接有一個(gè)移位器SHIFTER，也就是說(shuō)，操作數(shù)在經(jīng)過(guò)ALU的算邏操作前可先進(jìn)行移位處理，然后再經(jīng)ALU完成算邏運(yùn)算操作。移位包括：算術(shù)右移、邏輯左移、邏輯右移、循環(huán)左移以及循環(huán)右移。所以，μ’nSP™的指令系統(tǒng)里專(zhuān)有一組復(fù)合式的‘移位算邏操作’指令；此一條指令完成移位和算術(shù)邏輯操作兩項(xiàng)功能。程序設(shè)計(jì)者可利用這些復(fù)合式的指令，撰寫(xiě)更精簡(jiǎn)的程序代碼，進(jìn)而增加程序代碼密集度 (Code Density)。在微控制器應(yīng)用中，如何增加程序代碼密集度是非常重要的議題；提高程序代碼密集度意味著：減少程序代碼的大小，進(jìn)而減少ROM或FLASH的需求，以此降低系統(tǒng)成本與增加執(zhí)行效能。
標(biāo)簽： SPCE 061A 061 單片機(jī)
上傳時(shí)間： 2013-10-10
上傳用戶(hù)：星仔
摘要：本水位監(jiān)測(cè)報(bào)警器使用5V低壓直流電源（也可以用3節(jié)5號(hào)電池代替）就可以對(duì)5~15厘米的水位進(jìn)行監(jiān)測(cè)，用LED顯示和數(shù)碼管顯示水位，并可以對(duì)不再此范圍內(nèi)的水位發(fā)出報(bào)警。主要采用CD4066、74LS86、74LS32、CD4511芯片，再加上數(shù)碼管、蜂鳴器、發(fā)光二極管、電阻這些器件組成一個(gè)簡(jiǎn)單而靈敏的監(jiān)測(cè)報(bào)警電路，操作簡(jiǎn)單，接通電源即可工作。因?yàn)榇蟛糠蛛娐凡捎脭?shù)字電路，所以本水位監(jiān)測(cè)報(bào)警器還具有耗能低、準(zhǔn)確性高的特點(diǎn)。關(guān)鍵字：譯碼電路 報(bào)警電路 監(jiān)測(cè)電路 Abstract: The water level alarm monitoring the use of 5 V low-voltage DC power (can also use three batteries replaced on the 5th) will be able to 5 to 15 centimeters of water level monitoring, with LED display and digital display of water level, and this can no longer Within the scope of a water level alarm. Mainly CD4066, 74LS86, 74LS32, CD4511 chips, coupled with digital control, buzzer, light-emitting diode, the resistance of these devices composed of a simple and sensitive monitoring alarm circuits. Because the majority of circuits using digital circuitry, so the water level monitored alarm system also has low energy consumption, high accuracy of the characteristics. Keyword: Decoding circuit alarm circuit monitoring circuit
標(biāo)簽： 水位 監(jiān)測(cè)報(bào)警 系統(tǒng)原理
上傳時(shí)間： 2013-11-05
上傳用戶(hù)：王慶才
基于PIC單片機(jī)的低功耗讀卡器硬件設(shè)計(jì):本文提出了一個(gè)完整的基于串口的智能讀卡器子系統(tǒng)設(shè)計(jì)方案并將其實(shí)現(xiàn)。讀卡器的設(shè)計(jì)突出了小型化的要求，全部器件使用貼片封裝。為了減小讀卡器的體積，設(shè)計(jì)中還使用了串口竊電的技術(shù)，使用串口信號(hào)線直接給讀卡器供電。為此，讀卡器使用了省電的設(shè)計(jì)，采用了省電的集成電路，并大膽簡(jiǎn)化了許多傳統(tǒng)的設(shè)計(jì)電路。關(guān)鍵字： 讀卡器， 單片機(jī)， 串口竊電 Abstract： This paper aims to put forward a complete design of Smart IC card reader based onSerial Port and propose the way of realizing it for the purpose of Network Security. SMD isadopted to make Smart IC reader smaller in this design. To reduce the volume of Smart ICreader， Serial Port powered technology is employed to get power from the signal line of Serial Port. For this reason， low-power consumption components are adopted in the design and some traditional designs are simplified to reduce the power consumption.Keywords： Card Reader； Single-chip Computer； Serial Port Powered IC 卡系統(tǒng)保存了加密算法所需要的工作密鑰，供加密算法對(duì)網(wǎng)絡(luò)上傳輸?shù)臄?shù)據(jù)加密使用，是整個(gè)系統(tǒng)網(wǎng)絡(luò)安全的核心。在IC 卡子系統(tǒng)中，讀卡器是一個(gè)重要的部分。它起著管理IC卡、在IC 卡和PC或網(wǎng)絡(luò)計(jì)算機(jī)間傳遞數(shù)據(jù)的重要作用。本文以一片PIC單片機(jī)為核心完成了基于RS232 串口的讀卡器的硬件設(shè)計(jì)。
上傳時(shí)間： 2014-04-14
上傳用戶(hù)：wanghui2438
基于單片機(jī)控制的二氧化碳濃度測(cè)試計(jì):基于CDM4161二氧化碳?xì)怏w濃度測(cè)試模塊以及ATtiny26單片機(jī),提出了一種二氧化碳濃度測(cè)試計(jì)的設(shè)計(jì)方案。該方案具有硬件電路簡(jiǎn)單、成本低、可靠性高、測(cè)量準(zhǔn)確等優(yōu)點(diǎn)，具有較高的實(shí)用價(jià)值。 Abstract: Abstract：A desigh scheme of CO2 concentration meter based on CDM4161carbon dioxide concentration test module and ATtiny26micro-controller is presented in this paper.The design scheme features simple hardware circuit,low-cost,high reli-ability，accurate measurement and it has a high practical value.
標(biāo)簽： 單片機(jī)控制 二氧化碳 測(cè)試
上傳時(shí)間： 2013-11-14
上傳用戶(hù)：zjwangyichao
The solution presented in this paper and in the attached source files emulates the mostimportant SSC functions by using SW routines implemented in C. The code is focused onthe SAB C513, but will fit to all C500 derivatives.Beyond the low level software drivers a test shell is delivered. This shell allows a quicktest of the software drivers by an emulator or a starter kit demo board.
上傳時(shí)間： 2013-11-24
上傳用戶(hù)：363186
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