The first task at hand is to set up the endpoints appropriately for this example. The following code switches the CPU clock speed to 48 MHZ (since at power-on default it is 12 MHZ), and sets up EP2 as a Bulk OUT endpoint, 4x buffered of size 512, and EP6 as a Bulk IN endpoint, also 4x buffered of size 512. This set-up utilizes the maximum allotted 4-KB FIFO space. It also sets up the FIFOs for manual mode, word-wide operation, and goes through a FIFO reset and arming sequence to ensure that they are ready for data operations
標簽： appropriately The endpoints following
上傳時間： 2013-12-02
上傳用戶：dianxin61
The SDRAM controller is designed for the Virtex V300bg432-6. It s simulated with Micron SDRAM models. The design is verified with timing constraints at 115 MHZ.
標簽： SDRAM controller simulated designed
上傳時間： 2013-12-18
上傳用戶：yiwen213
All programs were tested using a breadboard containing a DS80C320, 32K Program memory, 32K Data memory, two 8-segment bar graph LEDs/drivers, and an 11.0592 MHZ crystal. The four 8-segment bar graph LEDs/drivers were connected to ports 1, and 3 to display their pins states.
標簽： breadboard containing 32K programs
上傳時間： 2016-03-29
上傳用戶：qq1604324866
CC1100是一種低成本真正單片的UHF收發器，為低功耗無線應用而設計。電路主要設定為在315、433、868和915MHZ的ISM（工業，科學和醫學）和SRD（短距離設備）頻率波段，也可以容易地設置為300-348 MHZ、400-464 MHZ和800-928 MHZ的其他頻率。 RF收發器集成了一個高度可配置的調制解調器。這個調制解調器支持不同的調制格式，其數據傳輸率可達500kbps。通過開啟集成在調制解調器上的前向誤差校正選項，能使性能得到提升。 CC1100為數據包處理、數據緩沖、突發數據傳輸、清晰信道評估、連接質量指示和電磁波激發提供廣泛的硬件支持。
上傳時間： 2014-10-09
上傳用戶：caixiaoxu26
A digital fi‘equeney meter designed with FPGA development software Q-~us 11 is introduced．The 1 Hz—l MHZ input measured pulse signals of the digital ii‘equency meter can be used for measuring frequency，period，pulse width and duty ratio，etc．The test results stably display O71 3 seven—segment numeric tubes，and the measuring ranges may be switched over automatically．The measuring error is equal to or less than 0．1％．
標簽： development introduced designed software
上傳時間： 2016-04-09
上傳用戶：stewart·
This example describes how to use the ADC and DMA to transfer continuously converted data from ADC to a data buffer. The ADC is configured to converts continuously ADC channel14. Each time an end of conversion occurs the DMA transfers, in circular mode, the converted data from ADC1 DR register to the ADC_ConvertedValue variable. The ADC1 clock is set to 14 MHZ.
標簽： continuously ADC describes converted
上傳時間： 2014-01-03
上傳用戶：徐孺
中國EPC標準草案（基本上是EPC C1G2的中文翻譯） 射頻識別協議- 第1類第2代UHF RFID 860兆赫-960兆赫通訊協議 EPC™ Radio-Frequency Identity Protocols Class-1 Generation-2 UHF RFID Protocol for Communications at 860 MHZ – 960 MHZ
標簽： EPC Radio-Frequency C1G2 8482
上傳時間： 2016-06-07
上傳用戶：上善若水
PTR2000 的Pin6 ( PWR) 與AT89C51 的P1. 0 相連,PTR2000 的Pin7 (TXEN) 與AT89C51 的P1. 1 相連,CS 直接接地,利用工作頻道1 ,即433. 92 MHZ. 通過匯編語言對其編程.
上傳時間： 2016-06-19
上傳用戶：hopy
LCM（RT-240128TA）顯示程序 */ /* LCM 控制芯片 T6963C 帶32KRAM */ /* MCU 型號: STC 89C52RD2 */ /* 時鐘頻率: 11.0592 MHZ */ /* 接口方式: 直接接口（總線方式
上傳時間： 2016-07-17
上傳用戶：xuan‘nian
高性能、低功耗的 AVR® 8 位微處理器 • 先進的 RISC 結構 – 133 條指令 – 大多數可以在一個時鐘周期內完成 – 32 x 8 通用工作寄存器 + 外設控制寄存器 – 全靜態工作 – 工作于16 MHZ 時性能高達16 MIPS
上傳時間： 2016-08-11
上傳用戶：趙云興
