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常用的嵌入式處理器有ARM、MIPS、PowerPC、X86、68K/Cold fire等，MIPS是Microprocessor without Inter-locked Pipeline Stages的縮寫，是由MIPS技術公司開發的一種處理器內核標準。目前有32位和64位MIPS芯片。PowerPC是早期Motorola公司和IBM公司聯合為Apple公司的MAC機開發的CPU芯片，商標權同時屬于IBM和Motorola兩家公司，并一度成為他們的主導產品。X86系列處理器起源于Intel架構的8080，然后發展出286、386、486直到現在的奔騰處理器乃至雙核處理器等。從嵌入式市場來看，486DX也應該是和ARM、68K、MIPS和SuperH齊名的5大嵌入式處理器之一。Motorola 68K是出現比較早的一款嵌入式處理器，采用的是CISC結構。
上傳時間： 2013-10-22
上傳用戶：dddddd55
The NCV7356 is a physical layer device for a single wire data linkcapable of operating with various Carrier Sense Multiple Accesswith Collision Resolution (CSMA/CR) protocols such as the BoschController Area Network (CAN) version 2.0. This serial data linknetwork is intended for use in applications where high data rate is notrequired and a lower data rate can achieve cost reductions in both thephysical media components and in the Microprocessor and/ordedicated logic devices which use the network.The network shall be able to operate in either the normal data ratemode or a high-speed data download mode for assembly line andservice data transfer operations. The high-speed mode is onlyintended to be operational when the bus is attached to an off-boardservice node. This node shall provide temporary bus electrical loadswhich facilitate higher speed operation. Such temporary loads shouldbe removed when not performing download operations.The bit rate for normal communications is typically 33 kbit/s, forhigh-speed transmissions like described above a typical bit rate of83 kbit/s is recommended. The NCV7356 features undervoltagelockout, timeout for faulty blocked input signals, output blankingtime in case of bus ringing and a very low sleep mode current.
上傳時間： 2013-10-24
上傳用戶：s藍莓汁
The LTC®3207/LTC3207-1 is a 600mA LED/Camera driverwhich illuminates 12 Universal LEDs (ULEDs) and onecamera fl ash LED. The ULEDs are considered universalbecause they may be individually turned on or off, setin general purpose output (GPO) mode, set to blink at aselected on-time and period, or gradate on and off at aselected gradation rate. This device also has an externalenable (ENU) pin that may be used to blink, gradate, orturn on/off the LEDs without using the I2C bus. This may beuseful if the Microprocessor is in sleep or standby mode. Ifused properly, these features may save valuable memoryspace, programming time, and reduce the I2C traffi c.
上傳時間： 2014-01-04
上傳用戶：LANCE
提出了一種以ARM微處理器為控制核心的遠程無線視頻監控終端的設計方案，其監控終端的硬件設計包括視頻采集處理、中央管理控制、無線傳輸3個模塊。并給出了監控終端的軟件開發平臺和開發模式的系統啟動代碼、嵌入式Linux系統移植以及驅動程序和應用程序。測試結果表明，該監控終端設計方案合理、有效，基本滿足監控需求。 Abstract: A remote wireless video monitoring terminal design， which uses ARM Microprocessor as its core control， is proposed in this paper.The hardware design of monitoring terminal system is composed of the video acquisition and processing module， the central management and control module， wireless transmission module.Meanwhile the monitoring terminal-s software development platform and development patterns are designed. Also the design of the system-s start codes， embedded Linux system-s transplantation process， driver and the corresponding applications are given. The results showed that the monitoring terminal design is reasonable， effective， basically meet monitoring requirements.
上傳時間： 2013-11-13
上傳用戶：wanqunsheng
This book is about the digital logic design of Microprocessors. It is intended to provide both an understanding of the basic principles of digital logic design, and how these fundamental principles are applied in the building of complex Microprocessor circuits using current technologies.
上傳時間： 2013-10-14
上傳用戶：leyesome
通過以太網遠程配置Nios II 處理器 應用筆記 Firmware in embedded hardware systems is frequently updated over the Ethernet. For embedded systems that comprise a discrete Microprocessor and the devices it controls, the firmware is the software image run by the Microprocessor. When the embedded system includes an FPGA, firmware updates include updates of the hardware image on the FPGA. If the FPGA includes a Nios® II soft processor, you can upgrade both the Nios II processor—as part of the FPGA image—and the software that the Nios II processor runs, in a single remote configuration session.
上傳時間： 2013-11-22
上傳用戶：chaisz
This application note describes how to build a system that can be used for determining theoptimal phase shift for a Double Data Rate (DDR) memory feedback clock. In this system, theDDR memory is controlled by a controller that attaches to either the OPB or PLB and is used inan embedded Microprocessor application. This reference system also uses a DCM that isconfigured so that the phase of its output clock can be changed while the system is running anda GPIO core that controls that phase shift. The GPIO output is controlled by a softwareapplication that can be run on a PowerPC® 405 or Microblaze™ Microprocessor.
上傳時間： 2014-11-26
上傳用戶：erkuizhang
SL811開發資料_包含源程序_電路圖_芯片資料:SL811HS Embedded USB Host/Slave Controller.The SL811HS is an Embedded USB Host/Slave Controller capable of communicate with either full-speed or low-speed USB peripherals. The SL811HS can interface to devices such as Microprocessors, microcontrollers, DSPs, or directly to a variety of buses such as ISA, PCMCIA, and others. The SL811HS USB Host Controller conforms to USB Specification 1.1.The SL811HS USB Host/Slave Controller incorporates USB Serial Interface functionality along with internal full-/low-speed transceivers.The SL811HS supports and operates in USB full-speed mode at 12 Mbps, or at low-speed 1.5-Mbps mode.The SL811HS data port and Microprocessor interface provide an 8-bit data path I/O or DMA bidirectional, with interrupt support to allow easy interface to standard Microprocessors or microcontrollers such as Motorola or Intel CPUs and many others. Internally,the SL811HS contains a 256-byte RAM data buffer which is used for control registers and data buffer.The available package types offered are a 28-pin PLCC (SL811HS) and a 48-pin TQFP package (SL811HST-AC). Both packages operate at 3.3 VDC. The I/O interface logic is 5V-tolerant.
上傳時間： 2013-12-22
上傳用戶：a82531317
uc/os-ii for 8051 This package provides the sources required to use the uC/OS-II v2.00 real time kernel on the 8051 processor. To use this package you will need the TASKING C Compiler toolset v6.0r1 or higher. For info on TASKING products you can contact our Web-site at: http://www.tasking.com Unzip the zipfile in the root of the drive where you also installed the uC/OS-II general sources. The following directories will be added: \SOFTWARE\UCOS-II\8051 This directory contains the Microprocessor specific source code \SOFTWARE\UCOS-II\ex1_8051r This directory contains the project files for the first example \SOFTWARE\UCOS-II\ex2_8051r This directory contains the project files for the second example
標簽： the provides required package
上傳時間： 2015-05-21
上傳用戶：ainimao
This package contains example software and associated documentation for the ColdFire MCF5249 Microprocessor. The software includes sample processor initialization routines for the MCF5249 running a M5249C3 evaluation board as well as the following sample applications: simple - empty application template fat - factory acceptance test for the M5249C3 The software has currently been built and tested under Metrowerks CodeWarrior
標簽： documentation associated ColdFire contains
上傳時間： 2013-12-10
上傳用戶：zaizaibang
